drm/amd/display: Add DCN2 changes to DML

Update DML (Display Mode Lib) to support DCN2
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

@@ -31,6 +31,7 @@
 #include "resource.h"
 #include "dcn10/dcn10_resource.h"
 #include "dcn10/dcn10_hubbub.h"
+#include "dml/dml1_display_rq_dlg_calc.h"
 
 #include "dcn_calc_math.h"
 
@@ -52,7 +53,13 @@
  * remain as-is as it provides us with a guarantee from HW that it is correct.
  */
 
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+/* Defaults from spreadsheet rev#247.
+ * RV2 delta: dram_clock_change_latency, max_num_dpp
+ */
+#else
 /* Defaults from spreadsheet rev#247 */
+#endif
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
 		/* latencies */
 		.sr_exit_time = 17, /*us*/

drivers/gpu/drm/amd/display/dc/dml/Makefile

@@ -33,13 +33,24 @@ endif
 dml_ccflags := -mhard-float -msse $(cc_stack_align)
 
 CFLAGS_display_mode_lib.o := $(dml_ccflags)
-CFLAGS_display_pipe_clocks.o := $(dml_ccflags)
+CFLAGS_display_mode_vba.o := $(dml_ccflags)
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
+CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
+endif
+ifdef CONFIG_DRM_AMD_DCN3AG
+CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags)
+endif
 CFLAGS_dml1_display_rq_dlg_calc.o := $(dml_ccflags)
 CFLAGS_display_rq_dlg_helpers.o := $(dml_ccflags)
 CFLAGS_dml_common_defs.o := $(dml_ccflags)
 
 DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
-	dml_common_defs.o
+	dml_common_defs.o display_mode_vba.o
+
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+DML += dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
+endif
 
 AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
 

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.h

+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN20_DISPLAY_MODE_VBA_H_
+#define _DCN20_DISPLAY_MODE_VBA_H_
+
+void dml20_recalculate(struct display_mode_lib *mode_lib);
+void dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h

+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML20_DISPLAY_RQ_DLG_CALC_H__
+#define __DML20_DISPLAY_RQ_DLG_CALC_H__
+
+#include "../dml_common_defs.h"
+#include "../display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+
+// Function: dml_rq_dlg_get_rq_reg
+//  Main entry point for test to get the register values out of this DML class.
+//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
+//  and then populate the rq_regs struct
+// Input:
+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
+// Output:
+//  rq_regs - struct that holds all the RQ registers field value.
+//            See also: <display_rq_regs_st>
+void dml20_rq_dlg_get_rq_reg(
+		struct display_mode_lib *mode_lib,
+		display_rq_regs_st *rq_regs,
+		const display_pipe_params_st pipe_param);
+
+
+// Function: dml_rq_dlg_get_dlg_reg
+//   Calculate and return DLG and TTU register struct given the system setting
+// Output:
+//  dlg_regs - output DLG register struct
+//  ttu_regs - output DLG TTU register struct
+// Input:
+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
+//  num_pipes - num of active "pipe" or "route"
+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+//           Added for legacy or unrealistic timing tests.
+void dml20_rq_dlg_get_dlg_reg(
+		struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		const bool cstate_en,
+		const bool pstate_en);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c

@@ -25,6 +25,19 @@
 
 #include "display_mode_lib.h"
 #include "dc_features.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#include "dcn20/display_mode_vba_20.h"
+#include "dcn20/display_rq_dlg_calc_20.h"
+#endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+const struct dml_funcs dml20_funcs = {
+	.validate = dml20_ModeSupportAndSystemConfigurationFull,
+	.recalculate = dml20_recalculate,
+	.rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg,
+	.rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg
+};
+#endif
 
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
@@ -34,6 +47,15 @@ void dml_init_instance(struct display_mode_lib *lib,
 	lib->soc = *soc_bb;
 	lib->ip = *ip_params;
 	lib->project = project;
+	switch (project) {
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	case DML_PROJECT_NAVI10:
+		lib->funcs = dml20_funcs;
+		break;
+#endif
+	default:
+		break;
+	}
 }
 
 const char *dml_get_status_message(enum dm_validation_status status)

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h

@@ -27,18 +27,43 @@
 
 
 #include "dml_common_defs.h"
-#include "dml1_display_rq_dlg_calc.h"
+#include "display_mode_vba.h"
 
 enum dml_project {
 	DML_PROJECT_UNDEFINED,
-	DML_PROJECT_RAVEN1
+	DML_PROJECT_RAVEN1,
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	DML_PROJECT_NAVI10,
+#endif
+};
+
+struct dml_funcs {
+	void (*rq_dlg_get_dlg_reg)(
+			struct display_mode_lib *mode_lib,
+			display_dlg_regs_st *dlg_regs,
+			display_ttu_regs_st *ttu_regs,
+			display_e2e_pipe_params_st *e2e_pipe_param,
+			const unsigned int num_pipes,
+			const unsigned int pipe_idx,
+			const bool cstate_en,
+			const bool pstate_en);
+	void (*rq_dlg_get_rq_reg)(
+		struct display_mode_lib *mode_lib,
+		display_rq_regs_st *rq_regs,
+		const display_pipe_params_st pipe_param);
+	void (*recalculate)(struct display_mode_lib *mode_lib);
+	void (*validate)(struct display_mode_lib *mode_lib);
 };
 
 struct display_mode_lib {
 	struct _vcs_dpi_ip_params_st ip;
 	struct _vcs_dpi_soc_bounding_box_st soc;
 	enum dml_project project;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	struct vba_vars_st vba;
+#endif
 	struct dal_logger *logger;
+	struct dml_funcs funcs;
 };
 
 void dml_init_instance(struct display_mode_lib *lib,

drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h

@@ -57,6 +57,7 @@ struct _vcs_dpi_voltage_scaling_st {
 	double dscclk_mhz;
 	double dcfclk_mhz;
 	double socclk_mhz;
+	double phyclk_d18_mhz;
 	double dram_speed_mts;
 	double fabricclk_mhz;
 	double dispclk_mhz;
@@ -97,6 +98,7 @@ struct _vcs_dpi_soc_bounding_box_st {
 	unsigned int num_banks;
 	unsigned int num_chans;
 	unsigned int vmm_page_size_bytes;
+	unsigned int hostvm_min_page_size_bytes;
 	double dram_clock_change_latency_us;
 	double writeback_dram_clock_change_latency_us;
 	unsigned int return_bus_width_bytes;
@@ -135,6 +137,21 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int writeback_luma_buffer_size_kbytes;
 	unsigned int writeback_chroma_buffer_size_kbytes;
 	unsigned int writeback_chroma_line_buffer_width_pixels;
+
+	unsigned int writeback_interface_buffer_size_kbytes;
+	unsigned int writeback_line_buffer_buffer_size;
+
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+	unsigned int writeback_10bpc420_supported;
+	double writeback_max_hscl_ratio;
+	double writeback_max_vscl_ratio;
+	double writeback_min_hscl_ratio;
+	double writeback_min_vscl_ratio;
+	unsigned int writeback_max_hscl_taps;
+	unsigned int writeback_max_vscl_taps;
+	unsigned int writeback_line_buffer_luma_buffer_size;
+	unsigned int writeback_line_buffer_chroma_buffer_size;
+#endif
 	unsigned int max_page_table_levels;
 	unsigned int max_num_dpp;
 	unsigned int max_num_otg;
@@ -152,6 +169,13 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int max_hscl_taps;
 	unsigned int max_vscl_taps;
 	unsigned int xfc_supported;
+	unsigned int ptoi_supported;
+	unsigned int gfx7_compat_tiling_supported;
+
+	bool odm_combine_4to1_supported;
+	bool dynamic_metadata_vm_enabled;
+	unsigned int max_num_hdmi_frl_outputs;
+
 	unsigned int xfc_fill_constant_bytes;
 	double dispclk_ramp_margin_percent;
 	double xfc_fill_bw_overhead_percent;
@@ -218,6 +242,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
 	unsigned int hsplit_grp;
 	unsigned char xfc_enable;
 	unsigned char xfc_slave;
+	unsigned char immediate_flip;
 	struct _vcs_dpi_display_xfc_params_st xfc_params;
 	//for vstartuplines calculation freesync
 	unsigned char v_total_min;
@@ -225,6 +250,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
 };
 struct writeback_st {
 	int wb_src_height;
+	int wb_src_width;
 	int wb_dst_width;
 	int wb_dst_height;
 	int wb_pixel_format;