Commit 72c70f01 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle

MIPS: Stop setting I6400 FTLBP

The FTLBP field in Config7 for the I6400 is intended as chicken bits for
debugging rather than as a field that software actually makes use of.
For best performance, FTLBP should be left at its default value of 0
with all TLB writes hitting the FTLB by default.

Additionally, since set_ftlb_enable is called from decode_configs before
decode_config4 which determines the size of the TLBs, this was
previously always setting FTLBP=3 for a 3:1 FTLB:VTLB write ratio which
makes abysmal use of the available FTLB resources.

This effectively reverts b0c4e1b79d8a ("MIPS: Set up FTLB probability
for I6400").
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Fixes: b0c4e1b79d8a ("MIPS: Set up FTLB probability for I6400")
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14021/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3021773c
...@@ -660,8 +660,6 @@ ...@@ -660,8 +660,6 @@
#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) #define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
#define MIPS_CONF7_AR (_ULCAST_(1) << 16) #define MIPS_CONF7_AR (_ULCAST_(1) << 16)
/* FTLB probability bits for R6 */
#define MIPS_CONF7_FTLBP_SHIFT (18)
/* WatchLo* register definitions */ /* WatchLo* register definitions */
#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0) #define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
......
...@@ -555,13 +555,8 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable) ...@@ -555,13 +555,8 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
write_c0_config6(config & ~MIPS_CONF6_FTLBEN); write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
break; break;
case CPU_I6400: case CPU_I6400:
/* I6400 & related cores use Config7 to configure FTLB */ /* There's no way to disable the FTLB */
config = read_c0_config7(); return !enable;
/* Clear the old probability value */
config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
write_c0_config7(config | (calculate_ftlb_probability(c)
<< MIPS_CONF7_FTLBP_SHIFT));
break;
case CPU_LOONGSON3: case CPU_LOONGSON3:
/* Flush ITLB, DTLB, VTLB and FTLB */ /* Flush ITLB, DTLB, VTLB and FTLB */
write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
......
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