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Commit 7313cff4 authored by Matt Porter's avatar Matt Porter
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Merge bk://ppc.bkbits.net/for-linus-ppc 

into free.ph.ph.cox.net:/home/mporter/src/linux-2.5
parents 8564a0f8 e8ecd3ed
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Documentation/powerpc/mpc52xx.txt
View file @ 7313cff4
Linux 2.6.x on MPC52xx family
-----------------------------
For the latest info, go to http://www.246tNt.com/mpc52xx/state.txt
For the latest info, go to http://www.246tNt.com/mpc52xx/
To compile/use :
......@@ -37,12 +37,3 @@ Some remarks :
- Of course, I inspired myself from the 2.4 port. If you think I forgot to
mention you/your company in the copyright of some code, I'll correct it
ASAP.
- The codes wants the MBAR to be set at 0xf0000000 by the bootloader. It's
mapped 1:1 with the MMU. If for whatever reason, you want to change this,
beware that some code depends on the 0xf0000000 address and other depends
on the 1:1 mapping.
- Most of the code assumes that port multiplexing, frequency selection, ...
has already been done. IMHO this should be done as early as possible, in
the bootloader. If for whatever reason you can't do it there, do it in the
platform setup code (if U-Boot) or in the arch/ppc/boot/simple/... (if
DBug)
MAINTAINERS
View file @ 7313cff4
......@@ -1301,6 +1301,15 @@ W: http://www.penguinppc.org/
L: linuxppc-dev@lists.linuxppc.org
S: Maintained
LINUX FOR POWERPC EMBEDDED MPC52XX
P: Sylvain Munaut
M: tnt@246tNt.com
W: http://www.246tNt.com/mpc52xx/
W: http://www.penguinppc.org/
L: linuxppc-dev@ozlabs.org
L: linuxppc-embedded@ozlabs.org
S: Maintained
LINUX FOR POWERPC EMBEDDED PPC4XX
P: Matt Porter
M: mporter@kernel.crashing.org
......
arch/ppc/boot/simple/misc.c
View file @ 7313cff4
......@@ -48,7 +48,9 @@
* Val Henson has requested that Gemini doesn't wait for the
* user to edit the cmdline or not.
*/
#if (defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_VGA_CONSOLE)) \
#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
|| defined(CONFIG_VGA_CONSOLE) \
|| defined(CONFIG_SERIAL_MPC52xx_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
#endif
......
arch/ppc/kernel/cputable.c
View file @ 7313cff4
This diff is collapsed.
arch/ppc/platforms/lite5200.c
View file @ 7313cff4
......@@ -36,6 +36,8 @@
#include <asm/mpc52xx.h>
extern int powersave_nap;
/* Board data given by U-Boot */
bd_t __res;
EXPORT_SYMBOL(__res); /* For modules */
......@@ -64,25 +66,55 @@ struct ocp_def board_ocp[] = {
.vendor = OCP_VENDOR_INVALID
}
};
/* ======================================================================== */
/* Platform specific code */
/* ======================================================================== */
static int
icecube_show_cpuinfo(struct seq_file *m)
lite5200_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "machine\t\t: Freescale LITE5200\n");
return 0;
}
static void __init
icecube_setup_arch(void)
lite5200_setup_cpu(void)
{
struct mpc52xx_intr *intr;
u32 intr_ctrl;
/* Map zones */
intr = (struct mpc52xx_intr *)
ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
if (!intr) {
printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
goto unmap_regs;
}
/* IRQ[0-3] setup : IRQ0 - Level Active Low */
/* IRQ[1-3] - Level Active High */
intr_ctrl = in_be32(&intr->ctrl);
intr_ctrl &= ~0x00ff0000;
intr_ctrl |= 0x00c00000;
out_be32(&intr->ctrl, intr_ctrl);
/* Unmap reg zone */
unmap_regs:
if (intr) iounmap(intr);
}
static void __init
lite5200_setup_arch(void)
{
/* Add board OCP definitions */
mpc52xx_add_board_devices(board_ocp);
/* CPU & Port mux setup */
lite5200_setup_cpu();
}
void __init
......@@ -110,7 +142,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
initrd_end = r5 + KERNELBASE;
}
#endif
/* Load the command line */
if (r6) {
*(char *)(r7+KERNELBASE) = 0;
......@@ -120,14 +152,17 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
/* BAT setup */
mpc52xx_set_bat();
/* No ISA bus AFAIK */
isa_io_base = 0;
isa_mem_base = 0;
/* Powersave */
powersave_nap = 1; /* We allow this platform to NAP */
/* Setup the ppc_md struct */
ppc_md.setup_arch = icecube_setup_arch;
ppc_md.show_cpuinfo = icecube_show_cpuinfo;
ppc_md.setup_arch = lite5200_setup_arch;
ppc_md.show_cpuinfo = lite5200_show_cpuinfo;
ppc_md.show_percpuinfo = NULL;
ppc_md.init_IRQ = mpc52xx_init_irq;
ppc_md.get_irq = mpc52xx_get_irq;
......@@ -138,12 +173,12 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.restart = mpc52xx_restart;
ppc_md.power_off = mpc52xx_power_off;
ppc_md.halt = mpc52xx_halt;
/* No time keeper on the IceCube */
/* No time keeper on the LITE5200 */
ppc_md.time_init = NULL;
ppc_md.get_rtc_time = NULL;
ppc_md.set_rtc_time = NULL;
ppc_md.calibrate_decr = mpc52xx_calibrate_decr;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = mpc52xx_progress;
......
arch/ppc/platforms/mpc5200.c
View file @ 7313cff4
......@@ -16,6 +16,12 @@
#include <asm/ocp.h>
#include <asm/mpc52xx.h>
struct ocp_fs_i2c_data mpc5200_i2c_def = {
.flags = FS_I2C_CLOCK_5200,
};
/* Here is the core_ocp struct.
* With all the devices common to all board. Even if port multiplexing is
* not setup for them (if the user don't want them, just don't select the
......@@ -23,6 +29,24 @@
* board specific file.
*/
struct ocp_def core_ocp[] = {
{
.vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 0,
.paddr = MPC52xx_I2C1,
.irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C1 - Buggy */
.pm = OCP_CPM_NA,
.additions = &mpc5200_i2c_def,
},
{
.vendor = OCP_VENDOR_FREESCALE,
.function = OCP_FUNC_IIC,
.index = 1,
.paddr = MPC52xx_I2C2,
.irq = OCP_IRQ_NA, /* MPC52xx_IRQ_I2C2 - Buggy */
.pm = OCP_CPM_NA,
.additions = &mpc5200_i2c_def,
},
{ /* Terminating entry */
.vendor = OCP_VENDOR_INVALID
}
......
arch/ppc/syslib/mpc52xx_pic.c
View file @ 7313cff4
......@@ -114,7 +114,7 @@ mpc52xx_ic_ack(unsigned int irq)
/*
* Only some irqs are reset here, others in interrupting hardware.
*/
switch (irq) {
case MPC52xx_IRQ0:
val = in_be32(&intr->ctrl);
......@@ -180,13 +180,14 @@ void __init
mpc52xx_init_irq(void)
{
int i;
u32 intr_ctrl;
/* Remap the necessary zones */
intr = (struct mpc52xx_intr *)
ioremap(MPC52xx_INTR, sizeof(struct mpc52xx_intr));
sdma = (struct mpc52xx_sdma *)
ioremap(MPC52xx_SDMA, sizeof(struct mpc52xx_sdma));
if ((intr==NULL) || (sdma==NULL))
panic("Can't ioremap PIC/SDMA register for init_irq !");
......@@ -195,12 +196,13 @@ mpc52xx_init_irq(void)
out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
out_be32(&intr->ctrl,
0x0f000000 | /* clear IRQ 0-3 */
0x00c00000 | /* IRQ0: level-sensitive, active low */
intr_ctrl = in_be32(&intr->ctrl);
intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
0x00001000 | /* MEE master external enable */
0x00000000 | /* 0 means disable IRQ 0-3 */
0x00000001); /* CEb route critical normally */
0x00000001; /* CEb route critical normally */
out_be32(&intr->ctrl, intr_ctrl);
/* Zero a bunch of the priority settings. */
out_be32(&intr->per_pri1, 0);
......@@ -214,6 +216,14 @@ mpc52xx_init_irq(void)
irq_desc[i].handler = &mpc52xx_ic;
irq_desc[i].status = IRQ_LEVEL;
}
#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
for (i=0 ; i<4 ; i++) {
int mode;
mode = IRQn_MODE(intr_ctrl,i);
if ((mode == 0x1) || (mode == 0x2))
irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
}
}
int
......
arch/ppc/syslib/mpc52xx_setup.c
View file @ 7313cff4
/*
* arch/ppc/syslib/mpc52xx_common.c
* arch/ppc/syslib/mpc52xx_setup.c
*
* Common code for the boards based on Freescale MPC52xx embedded CPU.
*
......@@ -23,6 +23,7 @@
#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include <asm/ocp.h>
#include <asm/pgtable.h>
#include <asm/ppcboot.h>
extern bd_t __res;
......@@ -38,9 +39,9 @@ void
mpc52xx_restart(char *cmd)
{
struct mpc52xx_gpt* gpt0 = (struct mpc52xx_gpt*) MPC52xx_GPTx(0);
local_irq_disable();
/* Turn on the watchdog and wait for it to expire. It effectively
does a reset */
if (gpt0 != NULL) {
......@@ -99,24 +100,28 @@ mpc52xx_map_io(void)
#error "mpc52xx PSC for console not selected"
#endif
static void
mpc52xx_psc_putc(struct mpc52xx_psc * psc, unsigned char c)
{
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY));
out_8(&psc->mpc52xx_psc_buffer_8, c);
}
void
mpc52xx_progress(char *s, unsigned short hex)
{
struct mpc52xx_psc *psc = (struct mpc52xx_psc *)MPC52xx_CONSOLE;
char c;
/* Don't we need to disable serial interrupts ? */
while ((c = *s++) != 0) {
if (c == '\n') {
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY)) ;
out_8(&psc->mpc52xx_psc_buffer_8, '\r');
}
while (!(in_be16(&psc->mpc52xx_psc_status) &
MPC52xx_PSC_SR_TXRDY)) ;
out_8(&psc->mpc52xx_psc_buffer_8, c);
if (c == '\n')
mpc52xx_psc_putc(psc, '\r');
mpc52xx_psc_putc(psc, c);
}
mpc52xx_psc_putc(psc, '\r');
mpc52xx_psc_putc(psc, '\n');
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
......@@ -137,7 +142,7 @@ mpc52xx_find_end_of_memory(void)
/* Temp BAT2 mapping active when this is called ! */
mmap_ctl = (struct mpc52xx_mmap_ctl*) MPC52xx_MMAP_CTL;
sdram_config_0 = in_be32(&mmap_ctl->sdram0);
sdram_config_1 = in_be32(&mmap_ctl->sdram1);
......@@ -147,10 +152,8 @@ mpc52xx_find_end_of_memory(void)
if (((sdram_config_1 & 0x1f) >= 0x13) &&
((sdram_config_1 & 0xfff00000) == ramsize))
ramsize += 1 << ((sdram_config_1 & 0xf) + 17);
iounmap(mmap_ctl);
}
return ramsize;
}
......@@ -167,7 +170,7 @@ mpc52xx_calibrate_decr(void)
/* Get RTC & Clock manager modules */
struct mpc52xx_rtc *rtc;
struct mpc52xx_cdm *cdm;
rtc = (struct mpc52xx_rtc*)
ioremap(MPC52xx_RTC, sizeof(struct mpc52xx_rtc));
cdm = (struct mpc52xx_cdm*)
......@@ -206,7 +209,7 @@ mpc52xx_calibrate_decr(void)
__res.bi_intfreq = cpufreq;
__res.bi_ipbfreq = ipbfreq;
__res.bi_pcifreq = pcifreq;
/* Release mapping */
iounmap((void*)rtc);
iounmap((void*)cdm);
......
include/asm-ppc/mpc52xx.h
View file @ 7313cff4
This diff is collapsed.
include/asm-ppc/mpc52xx_psc.h
View file @ 7313cff4
......@@ -19,8 +19,8 @@
* kind, whether express or implied.
*/
#ifndef __MPC52xx_PSC_H__
#define __MPC52xx_PSC_H__
#ifndef __ASM_MPC52xx_PSC_H__
#define __ASM_MPC52xx_PSC_H__
#include <asm/types.h>
......@@ -95,97 +95,97 @@
/* Structure of the hardware registers */
struct mpc52xx_psc {
volatile u8 mode; /* PSC + 0x00 */
volatile u8 reserved0[3];
union { /* PSC + 0x04 */
volatile u16 status;
volatile u16 clock_select;
u8 mode; /* PSC + 0x00 */
u8 reserved0[3];
union { /* PSC + 0x04 */
u16 status;
u16 clock_select;
} sr_csr;
#define mpc52xx_psc_status sr_csr.status
#define mpc52xx_psc_clock_select sr_csr.clock_select
volatile u16 reserved1;
volatile u8 command; /* PSC + 0x08 */
volatile u8 reserved2[3];
union { /* PSC + 0x0c */
volatile u8 buffer_8;
volatile u16 buffer_16;
volatile u32 buffer_32;
#define mpc52xx_psc_clock_select sr_csr.clock_select
u16 reserved1;
u8 command; /* PSC + 0x08 */
u8 reserved2[3];
union { /* PSC + 0x0c */
u8 buffer_8;
u16 buffer_16;
u32 buffer_32;
} buffer;
#define mpc52xx_psc_buffer_8 buffer.buffer_8
#define mpc52xx_psc_buffer_16 buffer.buffer_16
#define mpc52xx_psc_buffer_32 buffer.buffer_32
union { /* PSC + 0x10 */
volatile u8 ipcr;
volatile u8 acr;
union { /* PSC + 0x10 */
u8 ipcr;
u8 acr;
} ipcr_acr;
#define mpc52xx_psc_ipcr ipcr_acr.ipcr
#define mpc52xx_psc_acr ipcr_acr.acr
volatile u8 reserved3[3];
union { /* PSC + 0x14 */
volatile u16 isr;
volatile u16 imr;
u8 reserved3[3];
union { /* PSC + 0x14 */
u16 isr;
u16 imr;
} isr_imr;
#define mpc52xx_psc_isr isr_imr.isr
#define mpc52xx_psc_imr isr_imr.imr
volatile u16 reserved4;
volatile u8 ctur; /* PSC + 0x18 */
volatile u8 reserved5[3];
volatile u8 ctlr; /* PSC + 0x1c */
volatile u8 reserved6[3];
volatile u16 ccr; /* PSC + 0x20 */
volatile u8 reserved7[14];
volatile u8 ivr; /* PSC + 0x30 */
volatile u8 reserved8[3];
volatile u8 ip; /* PSC + 0x34 */
volatile u8 reserved9[3];
volatile u8 op1; /* PSC + 0x38 */
volatile u8 reserved10[3];
volatile u8 op0; /* PSC + 0x3c */
volatile u8 reserved11[3];
volatile u32 sicr; /* PSC + 0x40 */
volatile u8 ircr1; /* PSC + 0x44 */
volatile u8 reserved13[3];
volatile u8 ircr2; /* PSC + 0x44 */
volatile u8 reserved14[3];
volatile u8 irsdr; /* PSC + 0x4c */
volatile u8 reserved15[3];
volatile u8 irmdr; /* PSC + 0x50 */
volatile u8 reserved16[3];
volatile u8 irfdr; /* PSC + 0x54 */
volatile u8 reserved17[3];
volatile u16 rfnum; /* PSC + 0x58 */
volatile u16 reserved18;
volatile u16 tfnum; /* PSC + 0x5c */
volatile u16 reserved19;
volatile u32 rfdata; /* PSC + 0x60 */
volatile u16 rfstat; /* PSC + 0x64 */
volatile u16 reserved20;
volatile u8 rfcntl; /* PSC + 0x68 */
volatile u8 reserved21[5];
volatile u16 rfalarm; /* PSC + 0x6e */
volatile u16 reserved22;
volatile u16 rfrptr; /* PSC + 0x72 */
volatile u16 reserved23;
volatile u16 rfwptr; /* PSC + 0x76 */
volatile u16 reserved24;
volatile u16 rflrfptr; /* PSC + 0x7a */
volatile u16 reserved25;
volatile u16 rflwfptr; /* PSC + 0x7e */
volatile u32 tfdata; /* PSC + 0x80 */
volatile u16 tfstat; /* PSC + 0x84 */
volatile u16 reserved26;
volatile u8 tfcntl; /* PSC + 0x88 */
volatile u8 reserved27[5];
volatile u16 tfalarm; /* PSC + 0x8e */
volatile u16 reserved28;
volatile u16 tfrptr; /* PSC + 0x92 */
volatile u16 reserved29;
volatile u16 tfwptr; /* PSC + 0x96 */
volatile u16 reserved30;
volatile u16 tflrfptr; /* PSC + 0x9a */
volatile u16 reserved31;
volatile u16 tflwfptr; /* PSC + 0x9e */
u16 reserved4;
u8 ctur; /* PSC + 0x18 */
u8 reserved5[3];
u8 ctlr; /* PSC + 0x1c */
u8 reserved6[3];
u16 ccr; /* PSC + 0x20 */
u8 reserved7[14];
u8 ivr; /* PSC + 0x30 */
u8 reserved8[3];
u8 ip; /* PSC + 0x34 */
u8 reserved9[3];
u8 op1; /* PSC + 0x38 */
u8 reserved10[3];
u8 op0; /* PSC + 0x3c */
u8 reserved11[3];
u32 sicr; /* PSC + 0x40 */
u8 ircr1; /* PSC + 0x44 */
u8 reserved13[3];
u8 ircr2; /* PSC + 0x44 */
u8 reserved14[3];
u8 irsdr; /* PSC + 0x4c */
u8 reserved15[3];
u8 irmdr; /* PSC + 0x50 */
u8 reserved16[3];
u8 irfdr; /* PSC + 0x54 */
u8 reserved17[3];
u16 rfnum; /* PSC + 0x58 */
u16 reserved18;
u16 tfnum; /* PSC + 0x5c */
u16 reserved19;
u32 rfdata; /* PSC + 0x60 */
u16 rfstat; /* PSC + 0x64 */
u16 reserved20;
u8 rfcntl; /* PSC + 0x68 */
u8 reserved21[5];
u16 rfalarm; /* PSC + 0x6e */
u16 reserved22;
u16 rfrptr; /* PSC + 0x72 */
u16 reserved23;
u16 rfwptr; /* PSC + 0x76 */
u16 reserved24;
u16 rflrfptr; /* PSC + 0x7a */
u16 reserved25;
u16 rflwfptr; /* PSC + 0x7e */
u32 tfdata; /* PSC + 0x80 */
u16 tfstat; /* PSC + 0x84 */
u16 reserved26;
u8 tfcntl; /* PSC + 0x88 */
u8 reserved27[5];
u16 tfalarm; /* PSC + 0x8e */
u16 reserved28;
u16 tfrptr; /* PSC + 0x92 */
u16 reserved29;
u16 tfwptr; /* PSC + 0x96 */
u16 reserved30;
u16 tflrfptr; /* PSC + 0x9a */
u16 reserved31;
u16 tflwfptr; /* PSC + 0x9e */
};
#endif /* __MPC52xx_PSC_H__ */
#endif /* __ASM_MPC52xx_PSC_H__ */
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