Skip to content

L
linux
Commit 7488185d authored by Olof Johansson's avatar Olof Johansson
Browse files
Options

Merge branch 'for-3.5/gpio-pinmux' of... 

Merge branch 'for-3.5/gpio-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/pinctrl

By Stephen Warren
via Stephen Warren
* 'for-3.5/gpio-pinmux' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
  pinctrl: tegra: error reporting cleanup
  pinctrl: tegra: debugfs enhancements
  pinctrl: tegra: refactor probe handling
  ARM: dt: tegra20: add pinmux to device tree
  ARM: dt: tegra cardhu: add pinmux to device tree
  ARM: tegra: Remove pre-pinctrl pinmux driver
  ARM: tegra: Switch to new pinctrl driver
  gpio: tegra: Hide tegra_gpio_enable/disable()
  ARM: tegra: seaboard: Don't gpio_request() ISL29018_IRQ
  gpio: tegra: configure pins during irq_set_type
  ARM: tegra: Remove VBUS_GPIO handling from board files
  usb: ehci-tegra: Add vbus_gpio to platform data
parents b664ae6f aef7704c
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2055 additions and 3334 deletions
arch/arm/boot/dts/tegra-cardhu.dts
View file @ 7488185d
......@@ -10,6 +10,50 @@ memory {
reg = < 0x80000000 0x40000000 >;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
};
};
serial@70006000 {
clock-frequency = < 408000000 >;
};
......
arch/arm/boot/dts/tegra-harmony.dts
View file @ 7488185d
......@@ -10,6 +10,230 @@ memory@0 {
reg = < 0x00000000 0x40000000 >;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata";
nvidia,function = "ide";
};
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
};
atc {
nvidia,pins = "atc";
nvidia,function = "nand";
};
atd {
nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
"spia", "spib", "spic";
nvidia,function = "gmi";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp";
nvidia,function = "crt";
};
csus {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap2 {
nvidia,pins = "dap2";
nvidia,function = "dap2";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
};
dta {
nvidia,pins = "dta", "dtd";
nvidia,function = "sdio2";
};
dtb {
nvidia,pins = "dtb", "dtc", "dte";
nvidia,function = "rsvd1";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gmc {
nvidia,pins = "gmc";
nvidia,function = "uartd";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa", "slxk";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint", "pta";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uarta";
};
kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "kbc";
};
lcsn {
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
"ld3", "ld4", "ld5", "ld6", "ld7",
"ld8", "ld9", "ld10", "ld11", "ld12",
"ld13", "ld14", "ld15", "ld16", "ld17",
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
"lhs", "lm0", "lm1", "lpp", "lpw0",
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
"lvs";
nvidia,function = "displaya";
};
owc {
nvidia,pins = "owc", "spdi", "spdo", "uac";
nvidia,function = "rsvd2";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdb {
nvidia,pins = "sdb", "sdc", "sdd";
nvidia,function = "pwm";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxc {
nvidia,pins = "slxc", "slxd";
nvidia,function = "spdif";
};
spid {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "irda";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
"cdev1", "dap1", "dtb", "gma", "gmb",
"gmc", "gmd", "gme", "gpu7", "gpv",
"i2cp", "pta", "rm", "slxa", "slxk",
"spia", "spib";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_cdev2 {
nvidia,pins = "cdev2", "csus", "spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_crtp {
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
"dtc", "dte", "dtf", "gpu", "sdio1",
"slxc", "slxd", "spdi", "spdo", "spig",
"uac", "uda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
};
conf_ddc {
nvidia,pins = "ddc", "dta", "dtd", "kbca",
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
"sdc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "owc", "sdb";
nvidia,tristate = <1>;
};
conf_irrx {
nvidia,pins = "irrx", "irtx", "sdd", "spic",
"spie", "spih", "uaa", "uab", "uad",
"uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
"lvs", "pmc";
nvidia,tristate = <0>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
};
};
};
pmc@7000f400 {
nvidia,invert-interrupt;
};
......
arch/arm/boot/dts/tegra-paz00.dts
View file @ 7488185d
......@@ -10,6 +10,226 @@ memory@0 {
reg = <0x00000000 0x20000000>;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata", "atc", "atd", "ate",
"dap2", "gmb", "gmc", "gmd", "spia",
"spib", "spic", "spid", "spie";
nvidia,function = "gmi";
};
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp";
nvidia,function = "crt";
};
csus {
nvidia,pins = "csus";
nvidia,function = "pllc_out1";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
};
dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
nvidia,function = "rsvd1";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gpu {
nvidia,pins = "gpu", "sdb", "sdd";
nvidia,function = "pwm";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa", "slxk";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint", "pta";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uarta";
};
kbca {
nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
nvidia,function = "kbc";
};
kbcb {
nvidia,pins = "kbcb", "kbcd";
nvidia,function = "sdio2";
};
lcsn {
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
"ld3", "ld4", "ld5", "ld6", "ld7",
"ld8", "ld9", "ld10", "ld11", "ld12",
"ld13", "ld14", "ld15", "ld16", "ld17",
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
"lhs", "lm0", "lm1", "lpp", "lpw0",
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
"lvs";
nvidia,function = "displaya";
};
owc {
nvidia,pins = "owc";
nvidia,function = "owr";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdc {
nvidia,pins = "sdc";
nvidia,function = "twc";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxc {
nvidia,pins = "slxc", "slxd";
nvidia,function = "spi4";
};
spdi {
nvidia,pins = "spdi", "spdo";
nvidia,function = "rsvd2";
};
spif {
nvidia,pins = "spif", "uac";
nvidia,function = "rsvd4";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "spdif";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
"cdev1", "dap1", "dap2", "dtf", "gma",
"gmb", "gmc", "gmd", "gme", "gpu",
"gpu7", "gpv", "i2cp", "pta", "rm",
"sdio1", "slxk", "spdo", "uac", "uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_cdev2 {
nvidia,pins = "cdev2";
nvidia,pull = <1>;
nvidia,tristate = <0>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_crtp {
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
"dtc", "dte", "slxa", "slxc", "slxd",
"spdi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
};
conf_csus {
nvidia,pins = "csus", "spia", "spib", "spid",
"spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_ddc {
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
"spic", "spig", "uaa", "uab";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
conf_dta {
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
"spie", "spih", "uad", "uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
};
conf_hdint {
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
"ld3", "ld4", "ld5", "ld6", "ld7",
"ld8", "ld9", "ld10", "ld11", "ld12",
"ld13", "ld14", "ld15", "ld16", "ld17",
"ldc", "ldi", "lhs", "lsc0", "lspi",
"lvs", "pmc";
nvidia,tristate = <0>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
};
conf_lcsn {
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
"lm0", "lm1", "lpp", "lpw0", "lpw1",
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "lvp1", "sdb";
nvidia,tristate = <1>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
};
};
};
i2c@7000c000 {
clock-frequency = <400000>;
......
arch/arm/boot/dts/tegra-seaboard.dts
View file @ 7488185d
......@@ -11,6 +11,249 @@ memory {
reg = < 0x00000000 0x40000000 >;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata";
nvidia,function = "ide";
};
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
};
atc {
nvidia,pins = "atc";
nvidia,function = "nand";
};
atd {
nvidia,pins = "atd", "ate", "gmb", "spia",
"spib", "spic";
nvidia,function = "gmi";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp", "lm1";
nvidia,function = "crt";
};
csus {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap2 {
nvidia,pins = "dap2";
nvidia,function = "dap2";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
ddc {
nvidia,pins = "ddc", "owc", "spdi", "spdo",
"uac";
nvidia,function = "rsvd2";
};
dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
nvidia,function = "vi";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gmc {
nvidia,pins = "gmc";
nvidia,function = "uartd";
};
gmd {
nvidia,pins = "gmd";
nvidia,function = "sflash";
};
gpu {
nvidia,pins = "gpu";
nvidia,function = "pwm";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa", "slxk";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
"lsck", "lsda", "pta";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uartb";
};
kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "kbc";
};
lcsn {
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
"lsdi", "lvp0";
nvidia,function = "rsvd4";
};
ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lpp", "lsc0",
"lspi", "lvp1", "lvs";
nvidia,function = "displaya";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdb {
nvidia,pins = "sdb", "sdc", "sdd";
nvidia,function = "sdio3";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxc {
nvidia,pins = "slxc", "slxd";
nvidia,function = "spdif";
};
spid {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "irda";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd",
"cdev1", "cdev2", "dap1", "dap2",
"dap4", "dtf", "gma", "gmc", "gmd",
"gme", "gpu", "gpu7", "i2cp", "irrx",
"irtx", "pta", "rm", "sdc", "sdd",
"slxd", "slxk", "spdi", "spdo", "uac",
"uad", "uca", "ucb", "uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_ate {
nvidia,pins = "ate", "csus", "dap3", "ddc",
"gpv", "owc", "slxc", "spib", "spid",
"spie";
nvidia,pull = <0>;
nvidia,tristate = <1>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_crtp {
nvidia,pins = "crtp", "gmb", "slxa", "spia",
"spig", "spih";
nvidia,pull = <2>;
nvidia,tristate = <1>;
};
conf_dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd";
nvidia,pull = <1>;
nvidia,tristate = <0>;
};
conf_dte {
nvidia,pins = "dte", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
"lvp0";
nvidia,tristate = <1>;
};
conf_kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf", "sdio1", "spic", "uaa",
"uab";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
"lvs", "pmc", "sdb";
nvidia,tristate = <0>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <31>;
nvidia,pull-up-strength = <31>;
nvidia,slew-rate-rising = <3>;
nvidia,slew-rate-falling = <3>;
};
};
};
i2c@7000c000 {
clock-frequency = <400000>;
......
arch/arm/boot/dts/tegra-trimslice.dts
View file @ 7488185d
......@@ -10,6 +10,236 @@ memory@0 {
reg = < 0x00000000 0x40000000 >;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata";
nvidia,function = "ide";
};
atb {
nvidia,pins = "atb", "gma";
nvidia,function = "sdio4";
};
atc {
nvidia,pins = "atc", "gmb";
nvidia,function = "nand";
};
atd {
nvidia,pins = "atd", "ate", "gme", "pta";
nvidia,function = "gmi";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp";
nvidia,function = "crt";
};
csus {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap2 {
nvidia,pins = "dap2";
nvidia,function = "dap2";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
ddc {
nvidia,pins = "ddc";
nvidia,function = "i2c2";
};
dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
nvidia,function = "vi";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gmc {
nvidia,pins = "gmc", "gmd";
nvidia,function = "sflash";
};
gpu {
nvidia,pins = "gpu";
nvidia,function = "uarta";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa", "slxk";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uartb";
};
kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "kbc";
};
lcsn {
nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
"ld3", "ld4", "ld5", "ld6", "ld7",
"ld8", "ld9", "ld10", "ld11", "ld12",
"ld13", "ld14", "ld15", "ld16", "ld17",
"ldc", "ldi", "lhp0", "lhp1", "lhp2",
"lhs", "lm0", "lm1", "lpp", "lpw0",
"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
"lsda", "lsdi", "lspi", "lvp0", "lvp1",
"lvs";
nvidia,function = "displaya";
};
owc {
nvidia,pins = "owc", "uac";
nvidia,function = "rsvd2";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdb {
nvidia,pins = "sdb", "sdc", "sdd";
nvidia,function = "pwm";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxc {
nvidia,pins = "slxc", "slxd";
nvidia,function = "sdio3";
};
spdi {
nvidia,pins = "spdi", "spdo";
nvidia,function = "spdif";
};
spia {
nvidia,pins = "spia", "spib", "spic";
nvidia,function = "spi2";
};
spid {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "irda";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atc", "atd", "ate",
"crtp", "dap2", "dap3", "dap4", "dta",
"dtb", "dtc", "dtd", "dte", "gmb",
"gme", "i2cp", "pta", "slxc", "slxd",
"spdi", "spdo", "uda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
};
conf_atb {
nvidia,pins = "atb", "cdev1", "dap1", "gma",
"gmc", "gmd", "gpu", "gpu7", "gpv",
"sdio1", "slxa", "slxk", "uac";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_cdev2 {
nvidia,pins = "cdev2", "csus", "spia", "spib",
"spid", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_ddc {
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
"lvp0", "pmc";
nvidia,tristate = <1>;
};
conf_irrx {
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
"kbcc", "kbcd", "kbce", "kbcf", "owc",
"spic", "spie", "spig", "spih", "uaa",
"uab", "uad", "uca", "ucb";
nvidia,pull = <2>;
nvidia,tristate = <1>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
"lvs", "sdb";
nvidia,tristate = <0>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
};
};
};
i2c@7000c000 {
clock-frequency = <400000>;
};
......
arch/arm/boot/dts/tegra-ventana.dts
View file @ 7488185d
......@@ -10,6 +10,236 @@ memory {
reg = < 0x00000000 0x40000000 >;
};
pinmux@70000000 {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
ata {
nvidia,pins = "ata";
nvidia,function = "ide";
};
atb {
nvidia,pins = "atb", "gma", "gme";
nvidia,function = "sdio4";
};
atc {
nvidia,pins = "atc";
nvidia,function = "nand";
};
atd {
nvidia,pins = "atd", "ate", "gmb", "spia",
"spib", "spic";
nvidia,function = "gmi";
};
cdev1 {
nvidia,pins = "cdev1";
nvidia,function = "plla_out";
};
cdev2 {
nvidia,pins = "cdev2";
nvidia,function = "pllp_out4";
};
crtp {
nvidia,pins = "crtp", "lm1";
nvidia,function = "crt";
};
csus {
nvidia,pins = "csus";
nvidia,function = "vi_sensor_clk";
};
dap1 {
nvidia,pins = "dap1";
nvidia,function = "dap1";
};
dap2 {
nvidia,pins = "dap2";
nvidia,function = "dap2";
};
dap3 {
nvidia,pins = "dap3";
nvidia,function = "dap3";
};
dap4 {
nvidia,pins = "dap4";
nvidia,function = "dap4";
};
ddc {
nvidia,pins = "ddc", "owc", "spdi", "spdo",
"uac";
nvidia,function = "rsvd2";
};
dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
nvidia,function = "vi";
};
dtf {
nvidia,pins = "dtf";
nvidia,function = "i2c3";
};
gmc {
nvidia,pins = "gmc";
nvidia,function = "uartd";
};
gmd {
nvidia,pins = "gmd";
nvidia,function = "sflash";
};
gpu {
nvidia,pins = "gpu";
nvidia,function = "pwm";
};
gpu7 {
nvidia,pins = "gpu7";
nvidia,function = "rtck";
};
gpv {
nvidia,pins = "gpv", "slxa", "slxk";
nvidia,function = "pcie";
};
hdint {
nvidia,pins = "hdint", "pta";
nvidia,function = "hdmi";
};
i2cp {
nvidia,pins = "i2cp";
nvidia,function = "i2cp";
};
irrx {
nvidia,pins = "irrx", "irtx";
nvidia,function = "uartb";
};
kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf";
nvidia,function = "kbc";
};
lcsn {
nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
"lsdi", "lvp0";
nvidia,function = "rsvd4";
};
ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lpp", "lpw0",
"lpw2", "lsc0", "lsc1", "lsck", "lsda",
"lspi", "lvp1", "lvs";
nvidia,function = "displaya";
};
pmc {
nvidia,pins = "pmc";
nvidia,function = "pwr_on";
};
rm {
nvidia,pins = "rm";
nvidia,function = "i2c1";
};
sdb {
nvidia,pins = "sdb", "sdc", "sdd", "slxc";
nvidia,function = "sdio3";
};
sdio1 {
nvidia,pins = "sdio1";
nvidia,function = "sdio1";
};
slxd {
nvidia,pins = "slxd";
nvidia,function = "spdif";
};
spid {
nvidia,pins = "spid", "spie", "spif";
nvidia,function = "spi1";
};
spig {
nvidia,pins = "spig", "spih";
nvidia,function = "spi2_alt";
};
uaa {
nvidia,pins = "uaa", "uab", "uda";
nvidia,function = "ulpi";
};
uad {
nvidia,pins = "uad";
nvidia,function = "irda";
};
uca {
nvidia,pins = "uca", "ucb";
nvidia,function = "uartc";
};
conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd",
"cdev1", "cdev2", "dap1", "dap2",
"dap4", "ddc", "dtf", "gma", "gmc",
"gme", "gpu", "gpu7", "i2cp", "irrx",
"irtx", "pta", "rm", "sdc", "sdd",
"slxc", "slxd", "slxk", "spdi", "spdo",
"uac", "uad", "uca", "ucb", "uda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
conf_ate {
nvidia,pins = "ate", "csus", "dap3", "gmd",
"gpv", "owc", "spia", "spib", "spic",
"spid", "spie", "spig";
nvidia,pull = <0>;
nvidia,tristate = <1>;
};
conf_ck32 {
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
nvidia,pull = <0>;
};
conf_crtp {
nvidia,pins = "crtp", "gmb", "slxa", "spih";
nvidia,pull = <2>;
nvidia,tristate = <1>;
};
conf_dta {
nvidia,pins = "dta", "dtb", "dtc", "dtd";
nvidia,pull = <1>;
nvidia,tristate = <0>;
};
conf_dte {
nvidia,pins = "dte", "spif";
nvidia,pull = <1>;
nvidia,tristate = <1>;
};
conf_hdint {
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
nvidia,tristate = <1>;
};
conf_kbca {
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
"kbce", "kbcf", "sdio1", "uaa", "uab";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
conf_lc {
nvidia,pins = "lc", "ls";
nvidia,pull = <2>;
};
conf_ld0 {
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
"ld5", "ld6", "ld7", "ld8", "ld9",
"ld10", "ld11", "ld12", "ld13", "ld14",
"ld15", "ld16", "ld17", "ldi", "lhp0",
"lhp1", "lhp2", "lhs", "lm0", "lpp",
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
"lvp1", "lvs", "pmc", "sdb";
nvidia,tristate = <0>;
};
conf_ld17_0 {
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
"ld23_22";
nvidia,pull = <1>;
};
};
};
i2c@7000c000 {
clock-frequency = <400000>;
......
arch/arm/mach-tegra/Makefile
View file @ 7488185d
......@@ -5,7 +5,6 @@ obj-y += io.o
obj-y += irq.o
obj-y += clock.o
obj-y += timer.o
obj-y += pinmux.o
obj-y += fuse.o
obj-y += pmc.o
obj-y += flowctrl.o
......@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pinmux-tegra20-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
......
arch/arm/mach-tegra/board-dt-tegra20.c
View file @ 7488185d
......@@ -47,15 +47,7 @@
#include "clock.h"
#include "devices.h"
void harmony_pinmux_init(void);
void paz00_pinmux_init(void);
void seaboard_pinmux_init(void);
void trimslice_pinmux_init(void);
void ventana_pinmux_init(void);
struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
......@@ -95,33 +87,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
{}
};
static struct {
char *machine;
void (*init)(void);
} pinmux_configs[] = {
{ "compulab,trimslice", trimslice_pinmux_init },
{ "nvidia,harmony", harmony_pinmux_init },
{ "compal,paz00", paz00_pinmux_init },
{ "nvidia,seaboard", seaboard_pinmux_init },
{ "nvidia,ventana", ventana_pinmux_init },
};
static void __init tegra_dt_init(void)
{
int i;
tegra_clk_init_from_table(tegra_dt_clk_init_table);
for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
if (of_machine_is_compatible(pinmux_configs[i].machine)) {
pinmux_configs[i].init();
break;
}
}
WARN(i == ARRAY_SIZE(pinmux_configs),
"Unknown platform! Pinmuxing not initialized\n");
/*
* Finished with the static registrations now; fill in the missing
* devices
......
arch/arm/mach-tegra/board-harmony-pinmux.c
View file @ 7488185d
This diff is collapsed.
arch/arm/mach-tegra/board-paz00-pinmux.c
View file @ 7488185d
This diff is collapsed.
arch/arm/mach-tegra/board-pinmux.c
View file @ 7488185d
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
......@@ -15,75 +15,59 @@
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/notifier.h>
#include <linux/of.h>
#include <linux/string.h>
#include <mach/gpio-tegra.h>
#include <mach/pinmux.h>
#include "board-pinmux.h"
#include "devices.h"
struct tegra_board_pinmux_conf *confs[2];
static void tegra_board_pinmux_setup_gpios(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(confs); i++) {
if (!confs[i])
continue;
tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
}
}
static void tegra_board_pinmux_setup_pinmux(void)
{
int i;
unsigned long tegra_pincfg_pullnone_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
for (i = 0; i < ARRAY_SIZE(confs); i++) {
if (!confs[i])
continue;
unsigned long tegra_pincfg_pullnone_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
unsigned long tegra_pincfg_pullnone_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
};
if (confs[i]->drives)
tegra_drive_pinmux_config_table(confs[i]->drives,
confs[i]->drive_count);
}
}
unsigned long tegra_pincfg_pullup_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
unsigned long event, void *vdev)
{
static bool had_gpio;
static bool had_pinmux;
unsigned long tegra_pincfg_pullup_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
struct device *dev = vdev;
const char *devname;
unsigned long tegra_pincfg_pullup_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
};
if (event != BUS_NOTIFY_BOUND_DRIVER)
return NOTIFY_DONE;
unsigned long tegra_pincfg_pulldown_driven[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
devname = dev_name(dev);
unsigned long tegra_pincfg_pulldown_tristate[2] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
tegra_board_pinmux_setup_gpios();
had_gpio = true;
} else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
tegra_board_pinmux_setup_pinmux();
had_pinmux = true;
}
unsigned long tegra_pincfg_pulldown_na[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
};
if (had_gpio && had_pinmux)
return NOTIFY_STOP_MASK;
else
return NOTIFY_DONE;
}
unsigned long tegra_pincfg_pullna_driven[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
};
static struct notifier_block nb = {
.notifier_call = tegra_board_pinmux_bus_notify,
unsigned long tegra_pincfg_pullna_tristate[1] = {
TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
};
static struct platform_device *devices[] = {
......@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
struct tegra_board_pinmux_conf *conf_b)
{
confs[0] = conf_a;
confs[1] = conf_b;
bus_register_notifier(&platform_bus_type, &nb);
if (conf_a)
pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
if (conf_b)
pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
if (!of_machine_is_compatible("nvidia,tegra20"))
platform_add_devices(devices, ARRAY_SIZE(devices));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
arch/arm/mach-tegra/board-pinmux.h
View file @ 7488185d
/*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
......@@ -15,21 +15,37 @@
#ifndef __MACH_TEGRA_BOARD_PINMUX_H
#define __MACH_TEGRA_BOARD_PINMUX_H
#define GPIO_DEV "tegra-gpio"
#define PINMUX_DEV "tegra-pinmux"
#include <linux/pinctrl/machine.h>
struct tegra_pingroup_config;
struct tegra_gpio_table;
#include <mach/pinconf-tegra.h>
struct tegra_board_pinmux_conf {
struct tegra_pingroup_config *pgs;
int pg_count;
#define PINMUX_DEV "tegra20-pinctrl"
#define TEGRA_MAP_MUX(_group_, _function_) \
PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
struct tegra_drive_pingroup_config *drives;
int drive_count;
#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
TEGRA_MAP_MUX(_group_, _function_), \
TEGRA_MAP_CONF(_group_, _pull_, _drive_)
struct tegra_gpio_table *gpios;
int gpio_count;
extern unsigned long tegra_pincfg_pullnone_driven[2];
extern unsigned long tegra_pincfg_pullnone_tristate[2];
extern unsigned long tegra_pincfg_pullnone_na[1];
extern unsigned long tegra_pincfg_pullup_driven[2];
extern unsigned long tegra_pincfg_pullup_tristate[2];
extern unsigned long tegra_pincfg_pullup_na[1];
extern unsigned long tegra_pincfg_pulldown_driven[2];
extern unsigned long tegra_pincfg_pulldown_tristate[2];
extern unsigned long tegra_pincfg_pulldown_na[1];
extern unsigned long tegra_pincfg_pullna_driven[1];
extern unsigned long tegra_pincfg_pullna_tristate[1];
struct tegra_board_pinmux_conf {
struct pinctrl_map *maps;
int map_count;
};
void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
......
arch/arm/mach-tegra/board-seaboard-pinmux.c
View file @ 7488185d
This diff is collapsed.
arch/arm/mach-tegra/board-seaboard.c
View file @ 7488185d
......@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/platform_data/tegra_usb.h>
#include <sound/wm8903.h>
......@@ -186,20 +187,10 @@ static struct i2c_board_info __initdata wm8903_device = {
static int seaboard_ehci_init(void)
{
int gpio_status;
struct tegra_ehci_platform_data *pdata;
gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
if (gpio_status < 0) {
pr_err("VBUS_USB1 request GPIO FAILED\n");
WARN_ON(1);
}
gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
if (gpio_status < 0) {
pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
WARN_ON(1);
}
gpio_set_value(TEGRA_GPIO_USB1, 1);
pdata = tegra_ehci1_device.dev.platform_data;
pdata->vbus_gpio = TEGRA_GPIO_USB1;
platform_device_register(&tegra_ehci1_device);
platform_device_register(&tegra_ehci3_device);
......@@ -209,9 +200,6 @@ static int seaboard_ehci_init(void)
static void __init seaboard_i2c_init(void)
{
gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
i2c_register_board_info(0, &isl29018_device, 1);
......@@ -261,7 +249,6 @@ static void __init tegra_kaen_init(void)
debug_uart_platform_data[0].irq = INT_UARTB;
seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
seaboard_common_init();
......
arch/arm/mach-tegra/board-trimslice.c
View file @ 7488185d
......@@ -25,6 +25,7 @@
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/platform_data/tegra_usb.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
......@@ -111,19 +112,13 @@ static void trimslice_i2c_init(void)
static void trimslice_usb_init(void)
{
int err;
struct tegra_ehci_platform_data *pdata;
platform_device_register(&tegra_ehci3_device);
pdata = tegra_ehci1_device.dev.platform_data;
pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
platform_device_register(&tegra_ehci3_device);
platform_device_register(&tegra_ehci2_device);
err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
"usb1mode");
if (err) {
pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
return;
}
platform_device_register(&tegra_ehci1_device);
}
......
arch/arm/mach-tegra/devices.c
View file @ 7488185d
......@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
};
struct platform_device tegra_pinmux_device = {
.name = "tegra-pinmux",
.name = "tegra20-pinctrl",
.id = -1,
.resource = pinmux_resource,
.num_resources = ARRAY_SIZE(pinmux_resource),
......@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
.operating_mode = TEGRA_USB_OTG,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ehci_platform_data tegra_ehci2_pdata = {
.phy_config = &tegra_ehci2_ulpi_phy_config,
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
struct tegra_ehci_platform_data tegra_ehci3_pdata = {
.operating_mode = TEGRA_USB_HOST,
.power_down_on_bus_suspend = 1,
.vbus_gpio = -1,
};
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
......
arch/arm/mach-tegra/include/mach/gpio-tegra.h
View file @ 7488185d
......@@ -25,13 +25,4 @@
#define TEGRA_NR_GPIOS INT_GPIO_NR
struct tegra_gpio_table {
int gpio; /* GPIO number */
bool enable; /* Enable for GPIO at init? */
};
void tegra_gpio_config(struct tegra_gpio_table *table, int num);
void tegra_gpio_enable(int gpio);
void tegra_gpio_disable(int gpio);
#endif
arch/arm/mach-tegra/include/mach/pinmux-tegra20.h deleted 100644 → 0
View file @ b664ae6f
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
*
* Copyright (C) 2010 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
#define __MACH_TEGRA_PINMUX_TEGRA20_H
enum tegra_pingroup {
TEGRA_PINGROUP_ATA = 0,
TEGRA_PINGROUP_ATB,
TEGRA_PINGROUP_ATC,
TEGRA_PINGROUP_ATD,
TEGRA_PINGROUP_ATE,
TEGRA_PINGROUP_CDEV1,
TEGRA_PINGROUP_CDEV2,
TEGRA_PINGROUP_CRTP,
TEGRA_PINGROUP_CSUS,
TEGRA_PINGROUP_DAP1,
TEGRA_PINGROUP_DAP2,
TEGRA_PINGROUP_DAP3,
TEGRA_PINGROUP_DAP4,
TEGRA_PINGROUP_DDC,
TEGRA_PINGROUP_DTA,
TEGRA_PINGROUP_DTB,
TEGRA_PINGROUP_DTC,
TEGRA_PINGROUP_DTD,
TEGRA_PINGROUP_DTE,
TEGRA_PINGROUP_DTF,
TEGRA_PINGROUP_GMA,
TEGRA_PINGROUP_GMB,
TEGRA_PINGROUP_GMC,
TEGRA_PINGROUP_GMD,
TEGRA_PINGROUP_GME,
TEGRA_PINGROUP_GPU,
TEGRA_PINGROUP_GPU7,
TEGRA_PINGROUP_GPV,
TEGRA_PINGROUP_HDINT,
TEGRA_PINGROUP_I2CP,
TEGRA_PINGROUP_IRRX,
TEGRA_PINGROUP_IRTX,
TEGRA_PINGROUP_KBCA,
TEGRA_PINGROUP_KBCB,
TEGRA_PINGROUP_KBCC,
TEGRA_PINGROUP_KBCD,
TEGRA_PINGROUP_KBCE,
TEGRA_PINGROUP_KBCF,
TEGRA_PINGROUP_LCSN,
TEGRA_PINGROUP_LD0,
TEGRA_PINGROUP_LD1,
TEGRA_PINGROUP_LD10,
TEGRA_PINGROUP_LD11,
TEGRA_PINGROUP_LD12,
TEGRA_PINGROUP_LD13,
TEGRA_PINGROUP_LD14,
TEGRA_PINGROUP_LD15,
TEGRA_PINGROUP_LD16,
TEGRA_PINGROUP_LD17,
TEGRA_PINGROUP_LD2,
TEGRA_PINGROUP_LD3,
TEGRA_PINGROUP_LD4,
TEGRA_PINGROUP_LD5,
TEGRA_PINGROUP_LD6,
TEGRA_PINGROUP_LD7,
TEGRA_PINGROUP_LD8,
TEGRA_PINGROUP_LD9,
TEGRA_PINGROUP_LDC,
TEGRA_PINGROUP_LDI,
TEGRA_PINGROUP_LHP0,
TEGRA_PINGROUP_LHP1,
TEGRA_PINGROUP_LHP2,
TEGRA_PINGROUP_LHS,
TEGRA_PINGROUP_LM0,
TEGRA_PINGROUP_LM1,
TEGRA_PINGROUP_LPP,
TEGRA_PINGROUP_LPW0,
TEGRA_PINGROUP_LPW1,
TEGRA_PINGROUP_LPW2,
TEGRA_PINGROUP_LSC0,
TEGRA_PINGROUP_LSC1,
TEGRA_PINGROUP_LSCK,
TEGRA_PINGROUP_LSDA,
TEGRA_PINGROUP_LSDI,
TEGRA_PINGROUP_LSPI,
TEGRA_PINGROUP_LVP0,
TEGRA_PINGROUP_LVP1,
TEGRA_PINGROUP_LVS,
TEGRA_PINGROUP_OWC,
TEGRA_PINGROUP_PMC,
TEGRA_PINGROUP_PTA,
TEGRA_PINGROUP_RM,
TEGRA_PINGROUP_SDB,
TEGRA_PINGROUP_SDC,
TEGRA_PINGROUP_SDD,
TEGRA_PINGROUP_SDIO1,
TEGRA_PINGROUP_SLXA,
TEGRA_PINGROUP_SLXC,
TEGRA_PINGROUP_SLXD,
TEGRA_PINGROUP_SLXK,
TEGRA_PINGROUP_SPDI,
TEGRA_PINGROUP_SPDO,
TEGRA_PINGROUP_SPIA,
TEGRA_PINGROUP_SPIB,
TEGRA_PINGROUP_SPIC,
TEGRA_PINGROUP_SPID,
TEGRA_PINGROUP_SPIE,
TEGRA_PINGROUP_SPIF,
TEGRA_PINGROUP_SPIG,
TEGRA_PINGROUP_SPIH,
TEGRA_PINGROUP_UAA,
TEGRA_PINGROUP_UAB,
TEGRA_PINGROUP_UAC,
TEGRA_PINGROUP_UAD,
TEGRA_PINGROUP_UCA,
TEGRA_PINGROUP_UCB,
TEGRA_PINGROUP_UDA,
/* these pin groups only have pullup and pull down control */
TEGRA_PINGROUP_CK32,
TEGRA_PINGROUP_DDRC,
TEGRA_PINGROUP_PMCA,
TEGRA_PINGROUP_PMCB,
TEGRA_PINGROUP_PMCC,
TEGRA_PINGROUP_PMCD,
TEGRA_PINGROUP_PMCE,
TEGRA_PINGROUP_XM2C,
TEGRA_PINGROUP_XM2D,
TEGRA_MAX_PINGROUP,
};
enum tegra_drive_pingroup {
TEGRA_DRIVE_PINGROUP_AO1 = 0,
TEGRA_DRIVE_PINGROUP_AO2,
TEGRA_DRIVE_PINGROUP_AT1,
TEGRA_DRIVE_PINGROUP_AT2,
TEGRA_DRIVE_PINGROUP_CDEV1,
TEGRA_DRIVE_PINGROUP_CDEV2,
TEGRA_DRIVE_PINGROUP_CSUS,
TEGRA_DRIVE_PINGROUP_DAP1,
TEGRA_DRIVE_PINGROUP_DAP2,
TEGRA_DRIVE_PINGROUP_DAP3,
TEGRA_DRIVE_PINGROUP_DAP4,
TEGRA_DRIVE_PINGROUP_DBG,
TEGRA_DRIVE_PINGROUP_LCD1,
TEGRA_DRIVE_PINGROUP_LCD2,
TEGRA_DRIVE_PINGROUP_SDMMC2,
TEGRA_DRIVE_PINGROUP_SDMMC3,
TEGRA_DRIVE_PINGROUP_SPI,
TEGRA_DRIVE_PINGROUP_UAA,
TEGRA_DRIVE_PINGROUP_UAB,
TEGRA_DRIVE_PINGROUP_UART2,
TEGRA_DRIVE_PINGROUP_UART3,
TEGRA_DRIVE_PINGROUP_VI1,
TEGRA_DRIVE_PINGROUP_VI2,
TEGRA_DRIVE_PINGROUP_XM2A,
TEGRA_DRIVE_PINGROUP_XM2C,
TEGRA_DRIVE_PINGROUP_XM2D,
TEGRA_DRIVE_PINGROUP_XM2CLK,
TEGRA_DRIVE_PINGROUP_MEMCOMP,
TEGRA_DRIVE_PINGROUP_SDIO1,
TEGRA_DRIVE_PINGROUP_CRT,
TEGRA_DRIVE_PINGROUP_DDC,
TEGRA_DRIVE_PINGROUP_GMA,
TEGRA_DRIVE_PINGROUP_GMB,
TEGRA_DRIVE_PINGROUP_GMC,
TEGRA_DRIVE_PINGROUP_GMD,
TEGRA_DRIVE_PINGROUP_GME,
TEGRA_DRIVE_PINGROUP_OWR,
TEGRA_DRIVE_PINGROUP_UAD,
TEGRA_MAX_DRIVE_PINGROUP,
};
#endif
arch/arm/mach-tegra/include/mach/pinmux-tegra30.h deleted 100644 → 0
View file @ b664ae6f
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
#define __MACH_TEGRA_PINMUX_TEGRA30_H
enum tegra_pingroup {
TEGRA_PINGROUP_ULPI_DATA0 = 0,
TEGRA_PINGROUP_ULPI_DATA1,
TEGRA_PINGROUP_ULPI_DATA2,
TEGRA_PINGROUP_ULPI_DATA3,
TEGRA_PINGROUP_ULPI_DATA4,
TEGRA_PINGROUP_ULPI_DATA5,
TEGRA_PINGROUP_ULPI_DATA6,
TEGRA_PINGROUP_ULPI_DATA7,
TEGRA_PINGROUP_ULPI_CLK,
TEGRA_PINGROUP_ULPI_DIR,
TEGRA_PINGROUP_ULPI_NXT,
TEGRA_PINGROUP_ULPI_STP,
TEGRA_PINGROUP_DAP3_FS,
TEGRA_PINGROUP_DAP3_DIN,
TEGRA_PINGROUP_DAP3_DOUT,
TEGRA_PINGROUP_DAP3_SCLK,
TEGRA_PINGROUP_GPIO_PV0,
TEGRA_PINGROUP_GPIO_PV1,
TEGRA_PINGROUP_SDMMC1_CLK,
TEGRA_PINGROUP_SDMMC1_CMD,
TEGRA_PINGROUP_SDMMC1_DAT3,
TEGRA_PINGROUP_SDMMC1_DAT2,
TEGRA_PINGROUP_SDMMC1_DAT1,
TEGRA_PINGROUP_SDMMC1_DAT0,
TEGRA_PINGROUP_GPIO_PV2,
TEGRA_PINGROUP_GPIO_PV3,
TEGRA_PINGROUP_CLK2_OUT,
TEGRA_PINGROUP_CLK2_REQ,
TEGRA_PINGROUP_LCD_PWR1,
TEGRA_PINGROUP_LCD_PWR2,
TEGRA_PINGROUP_LCD_SDIN,
TEGRA_PINGROUP_LCD_SDOUT,
TEGRA_PINGROUP_LCD_WR_N,
TEGRA_PINGROUP_LCD_CS0_N,
TEGRA_PINGROUP_LCD_DC0,
TEGRA_PINGROUP_LCD_SCK,
TEGRA_PINGROUP_LCD_PWR0,
TEGRA_PINGROUP_LCD_PCLK,
TEGRA_PINGROUP_LCD_DE,
TEGRA_PINGROUP_LCD_HSYNC,
TEGRA_PINGROUP_LCD_VSYNC,
TEGRA_PINGROUP_LCD_D0,
TEGRA_PINGROUP_LCD_D1,
TEGRA_PINGROUP_LCD_D2,
TEGRA_PINGROUP_LCD_D3,
TEGRA_PINGROUP_LCD_D4,
TEGRA_PINGROUP_LCD_D5,
TEGRA_PINGROUP_LCD_D6,
TEGRA_PINGROUP_LCD_D7,
TEGRA_PINGROUP_LCD_D8,
TEGRA_PINGROUP_LCD_D9,
TEGRA_PINGROUP_LCD_D10,
TEGRA_PINGROUP_LCD_D11,
TEGRA_PINGROUP_LCD_D12,
TEGRA_PINGROUP_LCD_D13,
TEGRA_PINGROUP_LCD_D14,
TEGRA_PINGROUP_LCD_D15,
TEGRA_PINGROUP_LCD_D16,
TEGRA_PINGROUP_LCD_D17,
TEGRA_PINGROUP_LCD_D18,
TEGRA_PINGROUP_LCD_D19,
TEGRA_PINGROUP_LCD_D20,
TEGRA_PINGROUP_LCD_D21,
TEGRA_PINGROUP_LCD_D22,
TEGRA_PINGROUP_LCD_D23,
TEGRA_PINGROUP_LCD_CS1_N,
TEGRA_PINGROUP_LCD_M1,
TEGRA_PINGROUP_LCD_DC1,
TEGRA_PINGROUP_HDMI_INT,
TEGRA_PINGROUP_DDC_SCL,
TEGRA_PINGROUP_DDC_SDA,
TEGRA_PINGROUP_CRT_HSYNC,
TEGRA_PINGROUP_CRT_VSYNC,
TEGRA_PINGROUP_VI_D0,
TEGRA_PINGROUP_VI_D1,
TEGRA_PINGROUP_VI_D2,
TEGRA_PINGROUP_VI_D3,
TEGRA_PINGROUP_VI_D4,
TEGRA_PINGROUP_VI_D5,
TEGRA_PINGROUP_VI_D6,
TEGRA_PINGROUP_VI_D7,
TEGRA_PINGROUP_VI_D8,
TEGRA_PINGROUP_VI_D9,
TEGRA_PINGROUP_VI_D10,
TEGRA_PINGROUP_VI_D11,
TEGRA_PINGROUP_VI_PCLK,
TEGRA_PINGROUP_VI_MCLK,
TEGRA_PINGROUP_VI_VSYNC,
TEGRA_PINGROUP_VI_HSYNC,
TEGRA_PINGROUP_UART2_RXD,
TEGRA_PINGROUP_UART2_TXD,
TEGRA_PINGROUP_UART2_RTS_N,
TEGRA_PINGROUP_UART2_CTS_N,
TEGRA_PINGROUP_UART3_TXD,
TEGRA_PINGROUP_UART3_RXD,
TEGRA_PINGROUP_UART3_CTS_N,
TEGRA_PINGROUP_UART3_RTS_N,
TEGRA_PINGROUP_GPIO_PU0,
TEGRA_PINGROUP_GPIO_PU1,
TEGRA_PINGROUP_GPIO_PU2,
TEGRA_PINGROUP_GPIO_PU3,
TEGRA_PINGROUP_GPIO_PU4,
TEGRA_PINGROUP_GPIO_PU5,
TEGRA_PINGROUP_GPIO_PU6,
TEGRA_PINGROUP_GEN1_I2C_SDA,
TEGRA_PINGROUP_GEN1_I2C_SCL,
TEGRA_PINGROUP_DAP4_FS,
TEGRA_PINGROUP_DAP4_DIN,
TEGRA_PINGROUP_DAP4_DOUT,
TEGRA_PINGROUP_DAP4_SCLK,
TEGRA_PINGROUP_CLK3_OUT,
TEGRA_PINGROUP_CLK3_REQ,
TEGRA_PINGROUP_GMI_WP_N,
TEGRA_PINGROUP_GMI_IORDY,
TEGRA_PINGROUP_GMI_WAIT,
TEGRA_PINGROUP_GMI_ADV_N,
TEGRA_PINGROUP_GMI_CLK,
TEGRA_PINGROUP_GMI_CS0_N,
TEGRA_PINGROUP_GMI_CS1_N,
TEGRA_PINGROUP_GMI_CS2_N,
TEGRA_PINGROUP_GMI_CS3_N,
TEGRA_PINGROUP_GMI_CS4_N,
TEGRA_PINGROUP_GMI_CS6_N,
TEGRA_PINGROUP_GMI_CS7_N,
TEGRA_PINGROUP_GMI_AD0,
TEGRA_PINGROUP_GMI_AD1,
TEGRA_PINGROUP_GMI_AD2,
TEGRA_PINGROUP_GMI_AD3,
TEGRA_PINGROUP_GMI_AD4,
TEGRA_PINGROUP_GMI_AD5,
TEGRA_PINGROUP_GMI_AD6,
TEGRA_PINGROUP_GMI_AD7,
TEGRA_PINGROUP_GMI_AD8,
TEGRA_PINGROUP_GMI_AD9,
TEGRA_PINGROUP_GMI_AD10,
TEGRA_PINGROUP_GMI_AD11,
TEGRA_PINGROUP_GMI_AD12,
TEGRA_PINGROUP_GMI_AD13,
TEGRA_PINGROUP_GMI_AD14,
TEGRA_PINGROUP_GMI_AD15,
TEGRA_PINGROUP_GMI_A16,
TEGRA_PINGROUP_GMI_A17,
TEGRA_PINGROUP_GMI_A18,
TEGRA_PINGROUP_GMI_A19,
TEGRA_PINGROUP_GMI_WR_N,
TEGRA_PINGROUP_GMI_OE_N,
TEGRA_PINGROUP_GMI_DQS,
TEGRA_PINGROUP_GMI_RST_N,
TEGRA_PINGROUP_GEN2_I2C_SCL,
TEGRA_PINGROUP_GEN2_I2C_SDA,
TEGRA_PINGROUP_SDMMC4_CLK,
TEGRA_PINGROUP_SDMMC4_CMD,
TEGRA_PINGROUP_SDMMC4_DAT0,
TEGRA_PINGROUP_SDMMC4_DAT1,
TEGRA_PINGROUP_SDMMC4_DAT2,
TEGRA_PINGROUP_SDMMC4_DAT3,
TEGRA_PINGROUP_SDMMC4_DAT4,
TEGRA_PINGROUP_SDMMC4_DAT5,
TEGRA_PINGROUP_SDMMC4_DAT6,
TEGRA_PINGROUP_SDMMC4_DAT7,
TEGRA_PINGROUP_SDMMC4_RST_N,
TEGRA_PINGROUP_CAM_MCLK,
TEGRA_PINGROUP_GPIO_PCC1,
TEGRA_PINGROUP_GPIO_PBB0,
TEGRA_PINGROUP_CAM_I2C_SCL,
TEGRA_PINGROUP_CAM_I2C_SDA,
TEGRA_PINGROUP_GPIO_PBB3,
TEGRA_PINGROUP_GPIO_PBB4,
TEGRA_PINGROUP_GPIO_PBB5,
TEGRA_PINGROUP_GPIO_PBB6,
TEGRA_PINGROUP_GPIO_PBB7,
TEGRA_PINGROUP_GPIO_PCC2,
TEGRA_PINGROUP_JTAG_RTCK,
TEGRA_PINGROUP_PWR_I2C_SCL,
TEGRA_PINGROUP_PWR_I2C_SDA,
TEGRA_PINGROUP_KB_ROW0,
TEGRA_PINGROUP_KB_ROW1,
TEGRA_PINGROUP_KB_ROW2,
TEGRA_PINGROUP_KB_ROW3,
TEGRA_PINGROUP_KB_ROW4,
TEGRA_PINGROUP_KB_ROW5,
TEGRA_PINGROUP_KB_ROW6,
TEGRA_PINGROUP_KB_ROW7,
TEGRA_PINGROUP_KB_ROW8,
TEGRA_PINGROUP_KB_ROW9,
TEGRA_PINGROUP_KB_ROW10,
TEGRA_PINGROUP_KB_ROW11,
TEGRA_PINGROUP_KB_ROW12,
TEGRA_PINGROUP_KB_ROW13,
TEGRA_PINGROUP_KB_ROW14,
TEGRA_PINGROUP_KB_ROW15,
TEGRA_PINGROUP_KB_COL0,
TEGRA_PINGROUP_KB_COL1,
TEGRA_PINGROUP_KB_COL2,
TEGRA_PINGROUP_KB_COL3,
TEGRA_PINGROUP_KB_COL4,
TEGRA_PINGROUP_KB_COL5,
TEGRA_PINGROUP_KB_COL6,
TEGRA_PINGROUP_KB_COL7,
TEGRA_PINGROUP_CLK_32K_OUT,
TEGRA_PINGROUP_SYS_CLK_REQ,
TEGRA_PINGROUP_CORE_PWR_REQ,
TEGRA_PINGROUP_CPU_PWR_REQ,
TEGRA_PINGROUP_PWR_INT_N,
TEGRA_PINGROUP_CLK_32K_IN,
TEGRA_PINGROUP_OWR,
TEGRA_PINGROUP_DAP1_FS,
TEGRA_PINGROUP_DAP1_DIN,
TEGRA_PINGROUP_DAP1_DOUT,
TEGRA_PINGROUP_DAP1_SCLK,
TEGRA_PINGROUP_CLK1_REQ,
TEGRA_PINGROUP_CLK1_OUT,
TEGRA_PINGROUP_SPDIF_IN,
TEGRA_PINGROUP_SPDIF_OUT,
TEGRA_PINGROUP_DAP2_FS,
TEGRA_PINGROUP_DAP2_DIN,
TEGRA_PINGROUP_DAP2_DOUT,
TEGRA_PINGROUP_DAP2_SCLK,
TEGRA_PINGROUP_SPI2_MOSI,
TEGRA_PINGROUP_SPI2_MISO,
TEGRA_PINGROUP_SPI2_CS0_N,
TEGRA_PINGROUP_SPI2_SCK,
TEGRA_PINGROUP_SPI1_MOSI,
TEGRA_PINGROUP_SPI1_SCK,
TEGRA_PINGROUP_SPI1_CS0_N,
TEGRA_PINGROUP_SPI1_MISO,
TEGRA_PINGROUP_SPI2_CS1_N,
TEGRA_PINGROUP_SPI2_CS2_N,
TEGRA_PINGROUP_SDMMC3_CLK,
TEGRA_PINGROUP_SDMMC3_CMD,
TEGRA_PINGROUP_SDMMC3_DAT0,
TEGRA_PINGROUP_SDMMC3_DAT1,
TEGRA_PINGROUP_SDMMC3_DAT2,
TEGRA_PINGROUP_SDMMC3_DAT3,
TEGRA_PINGROUP_SDMMC3_DAT4,
TEGRA_PINGROUP_SDMMC3_DAT5,
TEGRA_PINGROUP_SDMMC3_DAT6,
TEGRA_PINGROUP_SDMMC3_DAT7,
TEGRA_PINGROUP_PEX_L0_PRSNT_N,
TEGRA_PINGROUP_PEX_L0_RST_N,
TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
TEGRA_PINGROUP_PEX_WAKE_N,
TEGRA_PINGROUP_PEX_L1_PRSNT_N,
TEGRA_PINGROUP_PEX_L1_RST_N,
TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
TEGRA_PINGROUP_PEX_L2_PRSNT_N,
TEGRA_PINGROUP_PEX_L2_RST_N,
TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
TEGRA_PINGROUP_HDMI_CEC,
TEGRA_MAX_PINGROUP,
};
enum tegra_drive_pingroup {
TEGRA_DRIVE_PINGROUP_AO1 = 0,
TEGRA_DRIVE_PINGROUP_AO2,
TEGRA_DRIVE_PINGROUP_AT1,
TEGRA_DRIVE_PINGROUP_AT2,
TEGRA_DRIVE_PINGROUP_AT3,
TEGRA_DRIVE_PINGROUP_AT4,
TEGRA_DRIVE_PINGROUP_AT5,
TEGRA_DRIVE_PINGROUP_CDEV1,
TEGRA_DRIVE_PINGROUP_CDEV2,
TEGRA_DRIVE_PINGROUP_CSUS,
TEGRA_DRIVE_PINGROUP_DAP1,
TEGRA_DRIVE_PINGROUP_DAP2,
TEGRA_DRIVE_PINGROUP_DAP3,
TEGRA_DRIVE_PINGROUP_DAP4,
TEGRA_DRIVE_PINGROUP_DBG,
TEGRA_DRIVE_PINGROUP_LCD1,
TEGRA_DRIVE_PINGROUP_LCD2,
TEGRA_DRIVE_PINGROUP_SDIO2,
TEGRA_DRIVE_PINGROUP_SDIO3,
TEGRA_DRIVE_PINGROUP_SPI,
TEGRA_DRIVE_PINGROUP_UAA,
TEGRA_DRIVE_PINGROUP_UAB,
TEGRA_DRIVE_PINGROUP_UART2,
TEGRA_DRIVE_PINGROUP_UART3,
TEGRA_DRIVE_PINGROUP_VI1,
TEGRA_DRIVE_PINGROUP_SDIO1,
TEGRA_DRIVE_PINGROUP_CRT,
TEGRA_DRIVE_PINGROUP_DDC,
TEGRA_DRIVE_PINGROUP_GMA,
TEGRA_DRIVE_PINGROUP_GMB,
TEGRA_DRIVE_PINGROUP_GMC,
TEGRA_DRIVE_PINGROUP_GMD,
TEGRA_DRIVE_PINGROUP_GME,
TEGRA_DRIVE_PINGROUP_GMF,
TEGRA_DRIVE_PINGROUP_GMG,
TEGRA_DRIVE_PINGROUP_GMH,
TEGRA_DRIVE_PINGROUP_OWR,
TEGRA_DRIVE_PINGROUP_UAD,
TEGRA_DRIVE_PINGROUP_GPV,
TEGRA_DRIVE_PINGROUP_DEV3,
TEGRA_DRIVE_PINGROUP_CEC,
TEGRA_MAX_DRIVE_PINGROUP,
};
#endif
arch/arm/mach-tegra/include/mach/pinmux.h deleted 100644 → 0
View file @ b664ae6f
/*
* linux/arch/arm/mach-tegra/include/mach/pinmux.h
*
* Copyright (C) 2010 Google, Inc.
* Copyright (C) 2010,2011 Nvidia, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_PINMUX_H
#define __MACH_TEGRA_PINMUX_H
enum tegra_mux_func {
TEGRA_MUX_RSVD = 0x8000,
TEGRA_MUX_RSVD1 = 0x8000,
TEGRA_MUX_RSVD2 = 0x8001,
TEGRA_MUX_RSVD3 = 0x8002,
TEGRA_MUX_RSVD4 = 0x8003,
TEGRA_MUX_INVALID = 0x4000,
TEGRA_MUX_NONE = -1,
TEGRA_MUX_AHB_CLK,
TEGRA_MUX_APB_CLK,
TEGRA_MUX_AUDIO_SYNC,
TEGRA_MUX_CRT,
TEGRA_MUX_DAP1,
TEGRA_MUX_DAP2,
TEGRA_MUX_DAP3,
TEGRA_MUX_DAP4,
TEGRA_MUX_DAP5,
TEGRA_MUX_DISPLAYA,
TEGRA_MUX_DISPLAYB,
TEGRA_MUX_EMC_TEST0_DLL,
TEGRA_MUX_EMC_TEST1_DLL,
TEGRA_MUX_GMI,
TEGRA_MUX_GMI_INT,
TEGRA_MUX_HDMI,
TEGRA_MUX_I2C,
TEGRA_MUX_I2C2,
TEGRA_MUX_I2C3,
TEGRA_MUX_IDE,
TEGRA_MUX_IRDA,
TEGRA_MUX_KBC,
TEGRA_MUX_MIO,
TEGRA_MUX_MIPI_HS,
TEGRA_MUX_NAND,
TEGRA_MUX_OSC,
TEGRA_MUX_OWR,
TEGRA_MUX_PCIE,
TEGRA_MUX_PLLA_OUT,
TEGRA_MUX_PLLC_OUT1,
TEGRA_MUX_PLLM_OUT1,
TEGRA_MUX_PLLP_OUT2,
TEGRA_MUX_PLLP_OUT3,
TEGRA_MUX_PLLP_OUT4,
TEGRA_MUX_PWM,
TEGRA_MUX_PWR_INTR,
TEGRA_MUX_PWR_ON,
TEGRA_MUX_RTCK,
TEGRA_MUX_SDIO1,
TEGRA_MUX_SDIO2,
TEGRA_MUX_SDIO3,
TEGRA_MUX_SDIO4,
TEGRA_MUX_SFLASH,
TEGRA_MUX_SPDIF,
TEGRA_MUX_SPI1,
TEGRA_MUX_SPI2,
TEGRA_MUX_SPI2_ALT,
TEGRA_MUX_SPI3,
TEGRA_MUX_SPI4,
TEGRA_MUX_TRACE,
TEGRA_MUX_TWC,
TEGRA_MUX_UARTA,
TEGRA_MUX_UARTB,
TEGRA_MUX_UARTC,
TEGRA_MUX_UARTD,
TEGRA_MUX_UARTE,
TEGRA_MUX_ULPI,
TEGRA_MUX_VI,
TEGRA_MUX_VI_SENSOR_CLK,
TEGRA_MUX_XIO,
TEGRA_MUX_BLINK,
TEGRA_MUX_CEC,
TEGRA_MUX_CLK12,
TEGRA_MUX_DAP,
TEGRA_MUX_DAPSDMMC2,
TEGRA_MUX_DDR,
TEGRA_MUX_DEV3,
TEGRA_MUX_DTV,
TEGRA_MUX_VI_ALT1,
TEGRA_MUX_VI_ALT2,
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_EMC_DLL,
TEGRA_MUX_EXTPERIPH1,
TEGRA_MUX_EXTPERIPH2,
TEGRA_MUX_EXTPERIPH3,
TEGRA_MUX_GMI_ALT,
TEGRA_MUX_HDA,
TEGRA_MUX_HSI,
TEGRA_MUX_I2C4,
TEGRA_MUX_I2C5,
TEGRA_MUX_I2CPWR,
TEGRA_MUX_I2S0,
TEGRA_MUX_I2S1,
TEGRA_MUX_I2S2,
TEGRA_MUX_I2S3,
TEGRA_MUX_I2S4,
TEGRA_MUX_NAND_ALT,
TEGRA_MUX_POPSDIO4,
TEGRA_MUX_POPSDMMC4,
TEGRA_MUX_PWM0,
TEGRA_MUX_PWM1,
TEGRA_MUX_PWM2,
TEGRA_MUX_PWM3,
TEGRA_MUX_SATA,
TEGRA_MUX_SPI5,
TEGRA_MUX_SPI6,
TEGRA_MUX_SYSCLK,
TEGRA_MUX_VGP1,
TEGRA_MUX_VGP2,
TEGRA_MUX_VGP3,
TEGRA_MUX_VGP4,
TEGRA_MUX_VGP5,
TEGRA_MUX_VGP6,
TEGRA_MUX_SAFE,
TEGRA_MAX_MUX,
};
enum tegra_pullupdown {
TEGRA_PUPD_NORMAL = 0,
TEGRA_PUPD_PULL_DOWN,
TEGRA_PUPD_PULL_UP,
};
enum tegra_tristate {
TEGRA_TRI_NORMAL = 0,
TEGRA_TRI_TRISTATE = 1,
};
enum tegra_pin_io {
TEGRA_PIN_OUTPUT = 0,
TEGRA_PIN_INPUT = 1,
};
enum tegra_vddio {
TEGRA_VDDIO_BB = 0,
TEGRA_VDDIO_LCD,
TEGRA_VDDIO_VI,
TEGRA_VDDIO_UART,
TEGRA_VDDIO_DDR,
TEGRA_VDDIO_NAND,
TEGRA_VDDIO_SYS,
TEGRA_VDDIO_AUDIO,
TEGRA_VDDIO_SD,
TEGRA_VDDIO_CAM,
TEGRA_VDDIO_GMI,
TEGRA_VDDIO_PEXCTL,
TEGRA_VDDIO_SDMMC1,
TEGRA_VDDIO_SDMMC3,
TEGRA_VDDIO_SDMMC4,
};
struct tegra_pingroup_config {
int pingroup;
enum tegra_mux_func func;
enum tegra_pullupdown pupd;
enum tegra_tristate tristate;
};
enum tegra_slew {
TEGRA_SLEW_FASTEST = 0,
TEGRA_SLEW_FAST,
TEGRA_SLEW_SLOW,
TEGRA_SLEW_SLOWEST,
TEGRA_MAX_SLEW,
};
enum tegra_pull_strength {
TEGRA_PULL_0 = 0,
TEGRA_PULL_1,
TEGRA_PULL_2,
TEGRA_PULL_3,
TEGRA_PULL_4,
TEGRA_PULL_5,
TEGRA_PULL_6,
TEGRA_PULL_7,
TEGRA_PULL_8,
TEGRA_PULL_9,
TEGRA_PULL_10,
TEGRA_PULL_11,
TEGRA_PULL_12,
TEGRA_PULL_13,
TEGRA_PULL_14,
TEGRA_PULL_15,
TEGRA_PULL_16,
TEGRA_PULL_17,
TEGRA_PULL_18,
TEGRA_PULL_19,
TEGRA_PULL_20,
TEGRA_PULL_21,
TEGRA_PULL_22,
TEGRA_PULL_23,
TEGRA_PULL_24,
TEGRA_PULL_25,
TEGRA_PULL_26,
TEGRA_PULL_27,
TEGRA_PULL_28,
TEGRA_PULL_29,
TEGRA_PULL_30,
TEGRA_PULL_31,
TEGRA_MAX_PULL,
};
enum tegra_drive {
TEGRA_DRIVE_DIV_8 = 0,
TEGRA_DRIVE_DIV_4,
TEGRA_DRIVE_DIV_2,
TEGRA_DRIVE_DIV_1,
TEGRA_MAX_DRIVE,
};
enum tegra_hsm {
TEGRA_HSM_DISABLE = 0,
TEGRA_HSM_ENABLE,
};
enum tegra_schmitt {
TEGRA_SCHMITT_DISABLE = 0,
TEGRA_SCHMITT_ENABLE,
};
struct tegra_drive_pingroup_config {
int pingroup;
enum tegra_hsm hsm;
enum tegra_schmitt schmitt;
enum tegra_drive drive;
enum tegra_pull_strength pull_down;
enum tegra_pull_strength pull_up;
enum tegra_slew slew_rising;
enum tegra_slew slew_falling;
};
struct tegra_drive_pingroup_desc {
const char *name;
s16 reg_bank;
s16 reg;
};
struct tegra_pingroup_desc {
const char *name;
int funcs[4];
int func_safe;
int vddio;
enum tegra_pin_io io_default;
s16 tri_bank; /* Register bank the tri_reg exists within */
s16 mux_bank; /* Register bank the mux_reg exists within */
s16 pupd_bank; /* Register bank the pupd_reg exists within */
s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */
s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */
s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */
s8 tri_bit; /* offset into the TRISTATE_REG_* register bit */
s8 mux_bit; /* offset into the PIN_MUX_CTL_* register bit */
s8 pupd_bit; /* offset into the PULL_UPDOWN_REG_* register bit */
s8 lock_bit; /* offset of the LOCK bit into mux register bit */
s8 od_bit; /* offset of the OD bit into mux register bit */
s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
};
typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
int *pgdrive_max);
void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
int len);
void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
int len);
void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
int len);
void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
int len);
void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
int len, enum tegra_tristate tristate);
void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
int len, enum tegra_pullupdown pupd);
#endif
arch/arm/mach-tegra/pinmux-tegra20-tables.c deleted 100644 → 0
View file @ b664ae6f
This diff is collapsed.
arch/arm/mach-tegra/pinmux-tegra30-tables.c deleted 100644 → 0
View file @ b664ae6f
This diff is collapsed.
arch/arm/mach-tegra/pinmux.c deleted 100644 → 0
View file @ b664ae6f
This diff is collapsed.
arch/arm/mach-tegra/usb_phy.c
View file @ 7488185d
......@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
err = -ENXIO;
goto err1;
}
tegra_gpio_enable(ulpi_config->reset_gpio);
gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
gpio_direction_output(ulpi_config->reset_gpio, 0);
phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
......
drivers/gpio/gpio-tegra.c
View file @ 7488185d
......@@ -26,10 +26,10 @@
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/pinctrl/consumer.h>
#include <asm/mach/irq.h>
#include <mach/gpio-tegra.h>
#include <mach/iomap.h>
#include <mach/suspend.h>
......@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
tegra_gpio_writel(val, reg);
}
void tegra_gpio_enable(int gpio)
static void tegra_gpio_enable(int gpio)
{
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}
EXPORT_SYMBOL_GPL(tegra_gpio_enable);
void tegra_gpio_disable(int gpio)
static void tegra_gpio_disable(int gpio)
{
tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}
EXPORT_SYMBOL_GPL(tegra_gpio_disable);
int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
return pinctrl_request_gpio(offset);
}
void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
pinctrl_free_gpio(offset);
tegra_gpio_disable(offset);
}
static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
......@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
tegra_gpio_enable(offset);
return 0;
}
......@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
{
tegra_gpio_set(chip, offset, value);
tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
tegra_gpio_enable(offset);
return 0;
}
......@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
static struct gpio_chip tegra_gpio_chip = {
.label = "tegra-gpio",
.request = tegra_gpio_request,
.free = tegra_gpio_free,
.direction_input = tegra_gpio_direction_input,
.get = tegra_gpio_get,
.direction_output = tegra_gpio_direction_output,
.set = tegra_gpio_set,
.to_irq = tegra_gpio_to_irq,
.base = 0,
.ngpio = TEGRA_NR_GPIOS,
};
static void tegra_gpio_irq_ack(struct irq_data *d)
......@@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
tegra_gpio_enable(gpio);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
__irq_set_handler_locked(d->irq, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
......@@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void)
}
postcore_initcall(tegra_gpio_init);
void tegra_gpio_config(struct tegra_gpio_table *table, int num)
{
int i;
for (i = 0; i < num; i++) {
int gpio = table[i].gpio;
if (table[i].enable)
tegra_gpio_enable(gpio);
else
tegra_gpio_disable(gpio);
}
}
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
......
drivers/mmc/host/sdhci-tegra.c
View file @ 7488185d
......@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
"failed to allocate power gpio\n");
goto err_power_req;
}
tegra_gpio_enable(plat->power_gpio);
gpio_direction_output(plat->power_gpio, 1);
}
......@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
"failed to allocate cd gpio\n");
goto err_cd_req;
}
tegra_gpio_enable(plat->cd_gpio);
gpio_direction_input(plat->cd_gpio);
rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
......@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
"failed to allocate wp gpio\n");
goto err_wp_req;
}
tegra_gpio_enable(plat->wp_gpio);
gpio_direction_input(plat->wp_gpio);
}
......@@ -329,23 +326,17 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
clk_disable(pltfm_host->clk);
clk_put(pltfm_host->clk);
err_clk_get:
if (gpio_is_valid(plat->wp_gpio)) {
tegra_gpio_disable(plat->wp_gpio);
if (gpio_is_valid(plat->wp_gpio))
gpio_free(plat->wp_gpio);
}
err_wp_req:
if (gpio_is_valid(plat->cd_gpio))
free_irq(gpio_to_irq(plat->cd_gpio), host);
err_cd_irq_req:
if (gpio_is_valid(plat->cd_gpio)) {
tegra_gpio_disable(plat->cd_gpio);
if (gpio_is_valid(plat->cd_gpio))
gpio_free(plat->cd_gpio);
}
err_cd_req:
if (gpio_is_valid(plat->power_gpio)) {
tegra_gpio_disable(plat->power_gpio);
if (gpio_is_valid(plat->power_gpio))
gpio_free(plat->power_gpio);
}
err_power_req:
err_no_plat:
sdhci_pltfm_free(pdev);
......@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
sdhci_remove_host(host, dead);
if (gpio_is_valid(plat->wp_gpio)) {
tegra_gpio_disable(plat->wp_gpio);
if (gpio_is_valid(plat->wp_gpio))
gpio_free(plat->wp_gpio);
}
if (gpio_is_valid(plat->cd_gpio)) {
free_irq(gpio_to_irq(plat->cd_gpio), host);
tegra_gpio_disable(plat->cd_gpio);
gpio_free(plat->cd_gpio);
}
if (gpio_is_valid(plat->power_gpio)) {
tegra_gpio_disable(plat->power_gpio);
if (gpio_is_valid(plat->power_gpio))
gpio_free(plat->power_gpio);
}
clk_disable(pltfm_host->clk);
clk_put(pltfm_host->clk);
......
drivers/pinctrl/pinctrl-tegra.c
View file @ 7488185d
This diff is collapsed.
drivers/pinctrl/pinctrl-tegra.h
View file @ 7488185d
......@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
unsigned ngroups;
};
/**
* tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC.
* @soc_data: This pointer must be updated to point at a struct containing
* details of the SoC.
*/
typedef void (*tegra_pinctrl_soc_initf)(
const struct tegra_pinctrl_soc_data **soc_data);
/**
* tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
* @soc_data: This pointer will be updated to point at a struct containing
* details of Tegra20's pin controller.
*/
void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
/**
* tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
* @soc_data: This pointer will be updated to point at a struct containing
* details of Tegra30's pin controller.
*/
void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
int tegra_pinctrl_probe(struct platform_device *pdev,
const struct tegra_pinctrl_soc_data *soc_data);
int tegra_pinctrl_remove(struct platform_device *pdev);
#endif
drivers/pinctrl/pinctrl-tegra20.c
View file @ 7488185d
/*
* Pinctrl data for the NVIDIA Tegra20 pinmux
*
* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
*
* Derived from code:
* Copyright (C) 2010 Google, Inc.
......@@ -17,6 +17,8 @@
* more details.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
......@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
.ngroups = ARRAY_SIZE(tegra20_groups),
};
void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc)
static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
{
*soc = &tegra20_pinctrl;
return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
}
static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
{ .compatible = "nvidia,tegra20-pinmux", },
{ },
};
static struct platform_driver tegra20_pinctrl_driver = {
.driver = {
.name = "tegra20-pinctrl",
.owner = THIS_MODULE,
.of_match_table = tegra20_pinctrl_of_match,
},
.probe = tegra20_pinctrl_probe,
.remove = __devexit_p(tegra_pinctrl_remove),
};
static int __init tegra20_pinctrl_init(void)
{
return platform_driver_register(&tegra20_pinctrl_driver);
}
arch_initcall(tegra20_pinctrl_init);
static void __exit tegra20_pinctrl_exit(void)
{
platform_driver_unregister(&tegra20_pinctrl_driver);
}
module_exit(tegra20_pinctrl_exit);
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
drivers/pinctrl/pinctrl-tegra30.c
View file @ 7488185d
This diff is collapsed.
drivers/usb/host/ehci-tegra.c
View file @ 7488185d
This diff is collapsed.
include/linux/platform_data/tegra_usb.h
View file @ 7488185d
......@@ -26,6 +26,7 @@ struct tegra_ehci_platform_data {
/* power down the phy on bus suspend */
int power_down_on_bus_suspend;
void *phy_config;
int vbus_gpio;
};
#endif /* _TEGRA_USB_H_ */
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7