Commit 78a16d9f authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman

powerpc/perf: Avoid FAB_*_MATCH checks for power9

Since power9 does not support FAB_*_MATCH bits in MMCR1,
avoid these checks for power9. For this, patch factor out
code in isa207_get_constraint() to retain these checks
only for power8.

Patch also updates the comment in power9-pmu raw event
encode layout to remove FAB_*_MATCH.

Finally for power9, patch adds additional check for
threshold events when adding the thresh mask and value in
isa207_get_constraint().

fixes: 7ffd948f ('powerpc/perf: factor out power8 pmu functions')
fixes: 18201b20 ('powerpc/perf: power9 raw event format encoding')
Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 8d911904
...@@ -97,6 +97,28 @@ static unsigned long combine_shift(unsigned long pmc) ...@@ -97,6 +97,28 @@ static unsigned long combine_shift(unsigned long pmc)
return MMCR1_COMBINE_SHIFT(pmc); return MMCR1_COMBINE_SHIFT(pmc);
} }
static inline bool event_is_threshold(u64 event)
{
return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
}
static bool is_thresh_cmp_valid(u64 event)
{
unsigned int cmp, exp;
/*
* Check the mantissa upper two bits are not zero, unless the
* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
*/
cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
exp = cmp >> 7;
if (exp && (cmp & 0x60) == 0)
return false;
return true;
}
int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
{ {
unsigned int unit, pmc, cache, ebb; unsigned int unit, pmc, cache, ebb;
...@@ -163,28 +185,26 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) ...@@ -163,28 +185,26 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
} }
/* if (cpu_has_feature(CPU_FTR_ARCH_300)) {
* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
* the threshold control bits are used for the match value. mask |= CNST_THRESH_MASK;
*/ value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
if (event_is_fab_match(event)) { }
mask |= CNST_FAB_MATCH_MASK;
value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
} else { } else {
/* /*
* Check the mantissa upper two bits are not zero, unless the * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
* exponent is also zero. See the THRESH_CMP_MANTISSA doc. * the threshold control bits are used for the match value.
*/ */
unsigned int cmp, exp; if (event_is_fab_match(event)) {
mask |= CNST_FAB_MATCH_MASK;
cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
exp = cmp >> 7; } else {
if (!is_thresh_cmp_valid(event))
if (exp && (cmp & 0x60) == 0) return -1;
return -1;
mask |= CNST_THRESH_MASK; mask |= CNST_THRESH_MASK;
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
}
} }
if (!pmc && ebb) if (!pmc && ebb)
...@@ -279,7 +299,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev, ...@@ -279,7 +299,7 @@ int isa207_compute_mmcr(u64 event[], int n_ev,
* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
* the threshold bits are used for the match value. * the threshold bits are used for the match value.
*/ */
if (event_is_fab_match(event[i])) { if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
} else { } else {
......
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
* | | | | | * | | | | |
* | | *- IFM (Linux) | thresh start/stop OR FAB match -* * | | *- IFM (Linux) | thresh start/stop -*
* | *- BHRB (Linux) *sm * | *- BHRB (Linux) *sm
* *- EBB (Linux) * *- EBB (Linux)
* *
...@@ -50,11 +50,9 @@ ...@@ -50,11 +50,9 @@
* MMCR1[31] = pmc4combine[1] * MMCR1[31] = pmc4combine[1]
* *
* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
* # PM_MRK_FAB_RSP_MATCH * MMCR1[20:27] = thresh_ctl
* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
* # PM_MRK_FAB_RSP_MATCH_CYC * MMCR1[20:27] = thresh_ctl
* MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
* else * else
* MMCRA[48:55] = thresh_ctl (THRESH START/END) * MMCRA[48:55] = thresh_ctl (THRESH START/END)
* *
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment