Commit 79bd9937 authored by David S. Miller's avatar David S. Miller

[SPARC64]: Fix spitfire bugs in tlb flush and copy_page changes.

- VISEntry clobbers %g3, so have to do %asi stuff
  after we invoke it.
- Need to or in 0x10 to TLB flush addresses when
  flushing in secondary context
- Context register restore using wrong address register
- Spitfire not so tolerant of membar in delay slot.
Signed-off-by: default avatarDavid S. Miller <davem@redhat.com>
parent 5dd3733b
......@@ -167,15 +167,15 @@ copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
nop
9:
VISEntry
ldx [%g6 + TI_FLAGS], %g3
mov %o0, %g1
andcc %g3, _TIF_BLKCOMMIT, %g0
rd %asi, %g3
be,a,pt %icc, 1f
wr %g0, ASI_BLK_P, %asi
wr %g0, ASI_BLK_COMMIT_P, %asi
1: VISEntry
mov %o0, %g1
ldda [%o1] ASI_BLK_P, %f0
1: ldda [%o1] ASI_BLK_P, %f0
add %o1, 0x40, %o1
ldda [%o1] ASI_BLK_P, %f16
add %o1, 0x40, %o1
......
......@@ -59,14 +59,15 @@ __flush_tlb_pending:
1: sub %o1, (1 << 3), %o1
ldx [%o2 + %o1], %o3
andcc %o3, 1, %g0
andn %o3, 1, %o3
be,pn %icc, 2f
andn %o3, 1, %o3
or %o3, 0x10, %o3
stxa %g0, [%o3] ASI_IMMU_DEMAP
2: stxa %g0, [%o3] ASI_DMMU_DEMAP
membar #Sync
brnz,pt %o1, 1b
nop
flush %g6
stxa %g2, [%o2] ASI_DMMU
stxa %g2, [%o4] ASI_DMMU
flush %g6
retl
wrpr %g5, 0x0, %pstate
......@@ -395,8 +396,9 @@ xcall_flush_tlb_pending:
andn %g5, 0x1, %g5
stxa %g0, [%g5] ASI_IMMU_DEMAP
2: stxa %g0, [%g5] ASI_DMMU_DEMAP
membar #Sync
brnz,pt %g1, 1b
membar #Sync
nop
stxa %g2, [%g4] ASI_DMMU
retry
......
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