Commit 7b048c52 authored by Teemu Paasikivi's avatar Teemu Paasikivi Committed by John W. Linville

wl1271: Renamed IO functions

In preparation for integration of SDIO implementation renamed some IO
functions from wl1271_spi_* form to wl1271_*.
Signed-off-by: default avatarTeemu Paasikivi <ext-teemu.3.paasikivi@nokia.com>
Reviewed-by: default avatarJuuso Oikarinen <juuso.oikarinen@nokia.com>
Signed-off-by: default avatarJuuso Oikarinen <juuso.oikarinen@nokia.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 521a5b21
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_boot.h" #include "wl1271_boot.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#include "wl1271_event.h" #include "wl1271_event.h"
static struct wl1271_partition_set part_table[PART_TABLE_LEN] = { static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
...@@ -93,19 +94,19 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag) ...@@ -93,19 +94,19 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
u32 cpu_ctrl; u32 cpu_ctrl;
/* 10.5.0 run the firmware (I) */ /* 10.5.0 run the firmware (I) */
cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL); cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
/* 10.5.1 run the firmware (II) */ /* 10.5.1 run the firmware (II) */
cpu_ctrl |= flag; cpu_ctrl |= flag;
wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
} }
static void wl1271_boot_fw_version(struct wl1271 *wl) static void wl1271_boot_fw_version(struct wl1271 *wl)
{ {
struct wl1271_static_data static_data; struct wl1271_static_data static_data;
wl1271_spi_read(wl, wl->cmd_box_addr, wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
&static_data, sizeof(static_data), false); false);
strncpy(wl->chip.fw_ver, static_data.fw_version, strncpy(wl->chip.fw_ver, static_data.fw_version,
sizeof(wl->chip.fw_ver)); sizeof(wl->chip.fw_ver));
...@@ -164,7 +165,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, ...@@ -164,7 +165,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
memcpy(chunk, p, CHUNK_SIZE); memcpy(chunk, p, CHUNK_SIZE);
wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x", wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
p, addr); p, addr);
wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false); wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
chunk_num++; chunk_num++;
} }
...@@ -175,7 +176,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf, ...@@ -175,7 +176,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
memcpy(chunk, p, fw_data_len % CHUNK_SIZE); memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x", wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
fw_data_len % CHUNK_SIZE, p, addr); fw_data_len % CHUNK_SIZE, p, addr);
wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false); wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
kfree(chunk); kfree(chunk);
return 0; return 0;
...@@ -256,7 +257,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) ...@@ -256,7 +257,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
wl1271_debug(DEBUG_BOOT, wl1271_debug(DEBUG_BOOT,
"nvs burst write 0x%x: 0x%x", "nvs burst write 0x%x: 0x%x",
dest_addr, val); dest_addr, val);
wl1271_spi_write32(wl, dest_addr, val); wl1271_write32(wl, dest_addr, val);
nvs_ptr += 4; nvs_ptr += 4;
dest_addr += 4; dest_addr += 4;
...@@ -290,7 +291,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) ...@@ -290,7 +291,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
/* FIXME: In wl1271, we upload everything at once. /* FIXME: In wl1271, we upload everything at once.
No endianness handling needed here?! The ref driver doesn't do No endianness handling needed here?! The ref driver doesn't do
anything about it at this point */ anything about it at this point */
wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false); wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
kfree(nvs_aligned); kfree(nvs_aligned);
return 0; return 0;
...@@ -299,9 +300,9 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl) ...@@ -299,9 +300,9 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
static void wl1271_boot_enable_interrupts(struct wl1271 *wl) static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
{ {
enable_irq(wl->irq); enable_irq(wl->irq);
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL); wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
} }
static int wl1271_boot_soft_reset(struct wl1271 *wl) static int wl1271_boot_soft_reset(struct wl1271 *wl)
...@@ -310,13 +311,12 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl) ...@@ -310,13 +311,12 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
u32 boot_data; u32 boot_data;
/* perform soft reset */ /* perform soft reset */
wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET, wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
ACX_SLV_SOFT_RESET_BIT);
/* SOFT_RESET is self clearing */ /* SOFT_RESET is self clearing */
timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME); timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
while (1) { while (1) {
boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET); boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data); wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0) if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
break; break;
...@@ -332,10 +332,10 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl) ...@@ -332,10 +332,10 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
} }
/* disable Rx/Tx */ /* disable Rx/Tx */
wl1271_spi_write32(wl, ENABLE, 0x0); wl1271_write32(wl, ENABLE, 0x0);
/* disable auto calibration on start*/ /* disable auto calibration on start*/
wl1271_spi_write32(wl, SPARE_A2, 0xffff); wl1271_write32(wl, SPARE_A2, 0xffff);
return 0; return 0;
} }
...@@ -347,7 +347,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) ...@@ -347,7 +347,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT); wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
chip_id = wl1271_spi_read32(wl, CHIP_ID_B); chip_id = wl1271_read32(wl, CHIP_ID_B);
wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id); wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
...@@ -360,8 +360,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) ...@@ -360,8 +360,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
loop = 0; loop = 0;
while (loop++ < INIT_LOOP) { while (loop++ < INIT_LOOP) {
udelay(INIT_LOOP_DELAY); udelay(INIT_LOOP_DELAY);
interrupt = wl1271_spi_read32(wl, interrupt = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
ACX_REG_INTERRUPT_NO_CLEAR);
if (interrupt == 0xffffffff) { if (interrupt == 0xffffffff) {
wl1271_error("error reading hardware complete " wl1271_error("error reading hardware complete "
...@@ -370,8 +369,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) ...@@ -370,8 +369,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
} }
/* check that ACX_INTR_INIT_COMPLETE is enabled */ /* check that ACX_INTR_INIT_COMPLETE is enabled */
else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) { else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK, wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
WL1271_ACX_INTR_INIT_COMPLETE); WL1271_ACX_INTR_INIT_COMPLETE);
break; break;
} }
} }
...@@ -383,10 +382,10 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl) ...@@ -383,10 +382,10 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
} }
/* get hardware config command mail box */ /* get hardware config command mail box */
wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR); wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
/* get hardware config event mail box */ /* get hardware config event mail box */
wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR); wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
/* set the working partition to its "running" mode offset */ /* set the working partition to its "running" mode offset */
wl1271_set_partition(wl, &part_table[PART_WORK]); wl1271_set_partition(wl, &part_table[PART_WORK]);
...@@ -459,9 +458,9 @@ int wl1271_boot(struct wl1271 *wl) ...@@ -459,9 +458,9 @@ int wl1271_boot(struct wl1271 *wl)
wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
} }
wl1271_spi_write32(wl, PLL_PARAMETERS, clk); wl1271_write32(wl, PLL_PARAMETERS, clk);
pause = wl1271_spi_read32(wl, PLL_PARAMETERS); pause = wl1271_read32(wl, PLL_PARAMETERS);
wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause); wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
...@@ -470,10 +469,10 @@ int wl1271_boot(struct wl1271 *wl) ...@@ -470,10 +469,10 @@ int wl1271_boot(struct wl1271 *wl)
* 0x3ff (magic number ). How does * 0x3ff (magic number ). How does
* this work?! */ * this work?! */
pause |= WU_COUNTER_PAUSE_VAL; pause |= WU_COUNTER_PAUSE_VAL;
wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause); wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
/* Continue the ELP wake up sequence */ /* Continue the ELP wake up sequence */
wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL); wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
udelay(500); udelay(500);
wl1271_set_partition(wl, &part_table[PART_DRPW]); wl1271_set_partition(wl, &part_table[PART_DRPW]);
...@@ -483,18 +482,18 @@ int wl1271_boot(struct wl1271 *wl) ...@@ -483,18 +482,18 @@ int wl1271_boot(struct wl1271 *wl)
before taking DRPw out of reset */ before taking DRPw out of reset */
wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START); wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START); clk = wl1271_read32(wl, DRPW_SCRATCH_START);
wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk); wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
/* 2 */ /* 2 */
clk |= (REF_CLOCK << 1) << 4; clk |= (REF_CLOCK << 1) << 4;
wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk); wl1271_write32(wl, DRPW_SCRATCH_START, clk);
wl1271_set_partition(wl, &part_table[PART_WORK]); wl1271_set_partition(wl, &part_table[PART_WORK]);
/* Disable interrupts */ /* Disable interrupts */
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
ret = wl1271_boot_soft_reset(wl); ret = wl1271_boot_soft_reset(wl);
if (ret < 0) if (ret < 0)
...@@ -509,23 +508,22 @@ int wl1271_boot(struct wl1271 *wl) ...@@ -509,23 +508,22 @@ int wl1271_boot(struct wl1271 *wl)
* ACX_EEPROMLESS_IND_REG */ * ACX_EEPROMLESS_IND_REG */
wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG"); wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG, wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
ACX_EEPROMLESS_IND_REG);
tmp = wl1271_spi_read32(wl, CHIP_ID_B); tmp = wl1271_read32(wl, CHIP_ID_B);
wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp); wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
/* 6. read the EEPROM parameters */ /* 6. read the EEPROM parameters */
tmp = wl1271_spi_read32(wl, SCR_PAD2); tmp = wl1271_read32(wl, SCR_PAD2);
ret = wl1271_boot_write_irq_polarity(wl); ret = wl1271_boot_write_irq_polarity(wl);
if (ret < 0) if (ret < 0)
goto out; goto out;
/* FIXME: Need to check whether this is really what we want */ /* FIXME: Need to check whether this is really what we want */
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
WL1271_ACX_ALL_EVENTS_VECTOR); WL1271_ACX_ALL_EVENTS_VECTOR);
/* WL1271: The reference driver skips steps 7 to 10 (jumps directly /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
* to upload_fw) */ * to upload_fw) */
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "wl1271.h" #include "wl1271.h"
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#include "wl1271_acx.h" #include "wl1271_acx.h"
#include "wl12xx_80211.h" #include "wl12xx_80211.h"
#include "wl1271_cmd.h" #include "wl1271_cmd.h"
...@@ -57,13 +58,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len, ...@@ -57,13 +58,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
WARN_ON(len % 4 != 0); WARN_ON(len % 4 != 0);
wl1271_spi_write(wl, wl->cmd_box_addr, buf, len, false); wl1271_write(wl, wl->cmd_box_addr, buf, len, false);
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD); wl1271_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD);
timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT); timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT);
intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) { while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) {
if (time_after(jiffies, timeout)) { if (time_after(jiffies, timeout)) {
wl1271_error("command complete timeout"); wl1271_error("command complete timeout");
...@@ -73,13 +74,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len, ...@@ -73,13 +74,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
msleep(1); msleep(1);
intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR); intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
} }
/* read back the status code of the command */ /* read back the status code of the command */
if (res_len == 0) if (res_len == 0)
res_len = sizeof(struct wl1271_cmd_header); res_len = sizeof(struct wl1271_cmd_header);
wl1271_spi_read(wl, wl->cmd_box_addr, cmd, res_len, false); wl1271_read(wl, wl->cmd_box_addr, cmd, res_len, false);
status = le16_to_cpu(cmd->status); status = le16_to_cpu(cmd->status);
if (status != CMD_STATUS_SUCCESS) { if (status != CMD_STATUS_SUCCESS) {
...@@ -87,8 +88,8 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len, ...@@ -87,8 +88,8 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
ret = -EIO; ret = -EIO;
} }
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK, wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
WL1271_ACX_INTR_CMD_COMPLETE); WL1271_ACX_INTR_CMD_COMPLETE);
out: out:
return ret; return ret;
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include "wl1271.h" #include "wl1271.h"
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#include "wl1271_event.h" #include "wl1271_event.h"
#include "wl1271_ps.h" #include "wl1271_ps.h"
#include "wl12xx_80211.h" #include "wl12xx_80211.h"
...@@ -214,7 +215,7 @@ int wl1271_event_unmask(struct wl1271 *wl) ...@@ -214,7 +215,7 @@ int wl1271_event_unmask(struct wl1271 *wl)
void wl1271_event_mbox_config(struct wl1271 *wl) void wl1271_event_mbox_config(struct wl1271 *wl)
{ {
wl->mbox_ptr[0] = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR); wl->mbox_ptr[0] = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox); wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);
wl1271_debug(DEBUG_EVENT, "MBOX ptrs: 0x%x 0x%x", wl1271_debug(DEBUG_EVENT, "MBOX ptrs: 0x%x 0x%x",
...@@ -232,8 +233,8 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num) ...@@ -232,8 +233,8 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
return -EINVAL; return -EINVAL;
/* first we read the mbox descriptor */ /* first we read the mbox descriptor */
wl1271_spi_read(wl, wl->mbox_ptr[mbox_num], &mbox, wl1271_read(wl, wl->mbox_ptr[mbox_num], &mbox,
sizeof(struct event_mailbox), false); sizeof(struct event_mailbox), false);
/* process the descriptor */ /* process the descriptor */
ret = wl1271_event_process(wl, &mbox); ret = wl1271_event_process(wl, &mbox);
...@@ -241,7 +242,7 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num) ...@@ -241,7 +242,7 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
return ret; return ret;
/* then we let the firmware know it can go on...*/ /* then we let the firmware know it can go on...*/
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK); wl1271_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK);
return 0; return 0;
} }
...@@ -124,10 +124,10 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf, ...@@ -124,10 +124,10 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf,
void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf, void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf,
size_t len, bool fixed) size_t len, bool fixed)
{ {
wl1271_spi_read(wl, addr, buf, len, fixed); wl1271_spi_raw_read(wl, addr, buf, len, fixed);
} }
void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len, void wl1271_read(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed) bool fixed)
{ {
int physical; int physical;
...@@ -137,8 +137,8 @@ void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len, ...@@ -137,8 +137,8 @@ void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
wl1271_spi_raw_read(wl, physical, buf, len, fixed); wl1271_spi_raw_read(wl, physical, buf, len, fixed);
} }
void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len, void wl1271_write(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed) bool fixed)
{ {
int physical; int physical;
...@@ -147,12 +147,12 @@ void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len, ...@@ -147,12 +147,12 @@ void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
wl1271_spi_raw_write(wl, physical, buf, len, fixed); wl1271_spi_raw_write(wl, physical, buf, len, fixed);
} }
u32 wl1271_spi_read32(struct wl1271 *wl, int addr) u32 wl1271_read32(struct wl1271 *wl, int addr)
{ {
return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr)); return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr));
} }
void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val) void wl1271_write32(struct wl1271 *wl, int addr, u32 val)
{ {
wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val); wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val);
} }
...@@ -161,13 +161,13 @@ void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val) ...@@ -161,13 +161,13 @@ void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
{ {
/* write address >> 1 + 0x30000 to OCP_POR_CTR */ /* write address >> 1 + 0x30000 to OCP_POR_CTR */
addr = (addr >> 1) + 0x30000; addr = (addr >> 1) + 0x30000;
wl1271_spi_write32(wl, OCP_POR_CTR, addr); wl1271_write32(wl, OCP_POR_CTR, addr);
/* write value to OCP_POR_WDATA */ /* write value to OCP_POR_WDATA */
wl1271_spi_write32(wl, OCP_DATA_WRITE, val); wl1271_write32(wl, OCP_DATA_WRITE, val);
/* write 1 to OCP_CMD */ /* write 1 to OCP_CMD */
wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_WRITE); wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
} }
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
...@@ -177,14 +177,14 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr) ...@@ -177,14 +177,14 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
/* write address >> 1 + 0x30000 to OCP_POR_CTR */ /* write address >> 1 + 0x30000 to OCP_POR_CTR */
addr = (addr >> 1) + 0x30000; addr = (addr >> 1) + 0x30000;
wl1271_spi_write32(wl, OCP_POR_CTR, addr); wl1271_write32(wl, OCP_POR_CTR, addr);
/* write 2 to OCP_CMD */ /* write 2 to OCP_CMD */
wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_READ); wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
/* poll for data ready */ /* poll for data ready */
do { do {
val = wl1271_spi_read32(wl, OCP_DATA_READ); val = wl1271_read32(wl, OCP_DATA_READ);
} while (!(val & OCP_READY_MASK) && --timeout); } while (!(val & OCP_READY_MASK) && --timeout);
if (!timeout) { if (!timeout) {
......
...@@ -34,4 +34,33 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf, ...@@ -34,4 +34,33 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf,
void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf, void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf,
size_t len, bool fixed); size_t len, bool fixed);
/* Translated target IO */
void wl1271_read(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed);
void wl1271_write(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed);
u32 wl1271_read32(struct wl1271 *wl, int addr);
void wl1271_write32(struct wl1271 *wl, int addr, u32 val);
/* Top Register IO */
void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
int wl1271_set_partition(struct wl1271 *wl,
struct wl1271_partition_set *p);
static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
{
wl1271_raw_read(wl, addr, &wl->buffer_32,
sizeof(wl->buffer_32), false);
return wl->buffer_32;
}
static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
{
wl->buffer_32 = val;
wl1271_raw_write(wl, addr, &wl->buffer_32,
sizeof(wl->buffer_32), false);
}
#endif #endif
...@@ -38,6 +38,7 @@ ...@@ -38,6 +38,7 @@
#include "wl12xx_80211.h" #include "wl12xx_80211.h"
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#include "wl1271_event.h" #include "wl1271_event.h"
#include "wl1271_tx.h" #include "wl1271_tx.h"
#include "wl1271_rx.h" #include "wl1271_rx.h"
...@@ -386,8 +387,7 @@ static void wl1271_fw_status(struct wl1271 *wl, ...@@ -386,8 +387,7 @@ static void wl1271_fw_status(struct wl1271 *wl,
u32 total = 0; u32 total = 0;
int i; int i;
wl1271_spi_read(wl, FW_STATUS_ADDR, status, wl1271_read(wl, FW_STATUS_ADDR, status, sizeof(*status), false);
sizeof(*status), false);
wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, " wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, "
"drv_rx_counter = %d, tx_results_counter = %d)", "drv_rx_counter = %d, tx_results_counter = %d)",
...@@ -434,7 +434,7 @@ static void wl1271_irq_work(struct work_struct *work) ...@@ -434,7 +434,7 @@ static void wl1271_irq_work(struct work_struct *work)
if (ret < 0) if (ret < 0)
goto out; goto out;
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL); wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
wl1271_fw_status(wl, wl->fw_status); wl1271_fw_status(wl, wl->fw_status);
intr = le32_to_cpu(wl->fw_status->intr); intr = le32_to_cpu(wl->fw_status->intr);
...@@ -476,8 +476,8 @@ static void wl1271_irq_work(struct work_struct *work) ...@@ -476,8 +476,8 @@ static void wl1271_irq_work(struct work_struct *work)
} }
out_sleep: out_sleep:
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK)); WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
wl1271_ps_elp_sleep(wl); wl1271_ps_elp_sleep(wl);
out: out:
...@@ -664,7 +664,7 @@ static int wl1271_chip_wakeup(struct wl1271 *wl) ...@@ -664,7 +664,7 @@ static int wl1271_chip_wakeup(struct wl1271 *wl)
/* whal_FwCtrl_BootSm() */ /* whal_FwCtrl_BootSm() */
/* 0. read chip id from CHIP_ID */ /* 0. read chip id from CHIP_ID */
wl->chip.id = wl1271_spi_read32(wl, CHIP_ID_B); wl->chip.id = wl1271_read32(wl, CHIP_ID_B);
/* 1. check if chip id is valid */ /* 1. check if chip id is valid */
......
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_ps.h" #include "wl1271_ps.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#define WL1271_WAKEUP_TIMEOUT 500 #define WL1271_WAKEUP_TIMEOUT 500
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_rx.h" #include "wl1271_rx.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status, static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status,
u32 drv_rx_counter) u32 drv_rx_counter)
...@@ -166,7 +167,7 @@ static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length) ...@@ -166,7 +167,7 @@ static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length)
} }
buf = skb_put(skb, length); buf = skb_put(skb, length);
wl1271_spi_read(wl, WL1271_SLV_MEM_DATA, buf, length, true); wl1271_read(wl, WL1271_SLV_MEM_DATA, buf, length, true);
/* the data read starts with the descriptor */ /* the data read starts with the descriptor */
desc = (struct wl1271_rx_descriptor *) buf; desc = (struct wl1271_rx_descriptor *) buf;
...@@ -210,15 +211,13 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status) ...@@ -210,15 +211,13 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status)
wl->rx_mem_pool_addr.addr + 4; wl->rx_mem_pool_addr.addr + 4;
/* Choose the block we want to read */ /* Choose the block we want to read */
wl1271_spi_write(wl, WL1271_SLV_REG_DATA, wl1271_write(wl, WL1271_SLV_REG_DATA, &wl->rx_mem_pool_addr,
&wl->rx_mem_pool_addr, sizeof(wl->rx_mem_pool_addr), false);
sizeof(wl->rx_mem_pool_addr), false);
wl1271_rx_handle_data(wl, buf_size); wl1271_rx_handle_data(wl, buf_size);
wl->rx_counter++; wl->rx_counter++;
drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK; drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
wl1271_spi_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);
wl->rx_counter);
} }
} }
...@@ -90,37 +90,7 @@ void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf, ...@@ -90,37 +90,7 @@ void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf, void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
size_t len, bool fixed); size_t len, bool fixed);
/* Translated target IO */
void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed);
void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
bool fixed);
u32 wl1271_spi_read32(struct wl1271 *wl, int addr);
void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val);
/* Top Register IO */
void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
/* INIT and RESET words */ /* INIT and RESET words */
void wl1271_spi_reset(struct wl1271 *wl); void wl1271_spi_reset(struct wl1271 *wl);
void wl1271_spi_init(struct wl1271 *wl); void wl1271_spi_init(struct wl1271 *wl);
int wl1271_set_partition(struct wl1271 *wl,
struct wl1271_partition_set *p);
static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
{
wl1271_spi_raw_read(wl, addr, &wl->buffer_32,
sizeof(wl->buffer_32), false);
return wl->buffer_32;
}
static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
{
wl->buffer_32 = val;
wl1271_spi_raw_write(wl, addr, &wl->buffer_32,
sizeof(wl->buffer_32), false);
}
#endif /* __WL1271_SPI_H__ */ #endif /* __WL1271_SPI_H__ */
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include "wl1271.h" #include "wl1271.h"
#include "wl1271_spi.h" #include "wl1271_spi.h"
#include "wl1271_io.h"
#include "wl1271_reg.h" #include "wl1271_reg.h"
#include "wl1271_ps.h" #include "wl1271_ps.h"
#include "wl1271_tx.h" #include "wl1271_tx.h"
...@@ -165,11 +166,11 @@ static int wl1271_tx_send_packet(struct wl1271 *wl, struct sk_buff *skb, ...@@ -165,11 +166,11 @@ static int wl1271_tx_send_packet(struct wl1271 *wl, struct sk_buff *skb,
len = WL1271_TX_ALIGN(skb->len); len = WL1271_TX_ALIGN(skb->len);
/* perform a fixed address block write with the packet */ /* perform a fixed address block write with the packet */
wl1271_spi_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true); wl1271_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true);
/* write packet new counter into the write access register */ /* write packet new counter into the write access register */
wl->tx_packets_count++; wl->tx_packets_count++;
wl1271_spi_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count); wl1271_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count);
desc = (struct wl1271_tx_hw_descr *) skb->data; desc = (struct wl1271_tx_hw_descr *) skb->data;
wl1271_debug(DEBUG_TX, "tx id %u skb 0x%p payload %u (%u words)", wl1271_debug(DEBUG_TX, "tx id %u skb 0x%p payload %u (%u words)",
...@@ -375,8 +376,8 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count) ...@@ -375,8 +376,8 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count)
wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count); wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count);
/* read the tx results from the chipset */ /* read the tx results from the chipset */
wl1271_spi_read(wl, le32_to_cpu(memmap->tx_result), wl1271_read(wl, le32_to_cpu(memmap->tx_result),
wl->tx_res_if, sizeof(*wl->tx_res_if), false); wl->tx_res_if, sizeof(*wl->tx_res_if), false);
/* verify that the result buffer is not getting overrun */ /* verify that the result buffer is not getting overrun */
if (count > TX_HW_RESULT_QUEUE_LEN) { if (count > TX_HW_RESULT_QUEUE_LEN) {
...@@ -397,10 +398,10 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count) ...@@ -397,10 +398,10 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count)
} }
/* write host counter to chipset (to ack) */ /* write host counter to chipset (to ack) */
wl1271_spi_write32(wl, le32_to_cpu(memmap->tx_result) + wl1271_write32(wl, le32_to_cpu(memmap->tx_result) +
offsetof(struct wl1271_tx_hw_res_if, offsetof(struct wl1271_tx_hw_res_if,
tx_result_host_counter), tx_result_host_counter),
le32_to_cpu(wl->tx_res_if->tx_result_fw_counter)); le32_to_cpu(wl->tx_res_if->tx_result_fw_counter));
} }
/* caller must hold wl->mutex */ /* caller must hold wl->mutex */
......
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