Commit 7b0f47aa authored by Marcel Ziswiler's avatar Marcel Ziswiler Committed by Thierry Reding

ARM: tegra: apalis_t30: get rid of fake clocks simple bus

Get rid of the fake clocks simple bus and use node names as per the
actual schematics.
Signed-off-by: default avatarMarcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 200be313
......@@ -1097,25 +1097,16 @@ sdhci@78000600 {
mmc-ddr-1_8v;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk32k_in: clk@0 {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <32768>;
};
clk32k_in: xtal1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
clk16m: clk@1 {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "clk16m";
};
clk16m: osc4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
......
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