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Commit 7cd4a5eb authored by Tony Lindgren's avatar Tony Lindgren
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Merge branch 'omap-for-v4.15/fixes-dt' into omap-for-v4.15/fixes-v2

parents 124dcf79 bc686442
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Showing with 47 additions and 13 deletions
Documentation/devicetree/bindings/usb/am33xx-usb.txt
View file @ 7cd4a5eb
......@@ -95,6 +95,7 @@ usb: usb@47400000 {
reg = <0x47401300 0x100>;
reg-names = "phy";
ti,ctrl_mod = <&ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
......@@ -141,6 +142,7 @@ usb: usb@47400000 {
reg = <0x47401b00 0x100>;
reg-names = "phy";
ti,ctrl_mod = <&ctrl_mod>;
#phy-cells = <0>;
};
usb1: usb@47401800 {
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 7cd4a5eb
......@@ -630,6 +630,7 @@ usb0_phy: usb-phy@47401300 {
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
......@@ -678,6 +679,7 @@ usb1_phy: usb-phy@47401b00 {
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb1: usb@47401800 {
......
arch/arm/boot/dts/am4372.dtsi
View file @ 7cd4a5eb
......@@ -927,7 +927,8 @@ mcasp0: mcasp@48038000 {
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8 2>,
......@@ -941,7 +942,8 @@ mcasp1: mcasp@4803C000 {
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <82>, <83>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10 2>,
......
arch/arm/boot/dts/am437x-cm-t43.dts
View file @ 7cd4a5eb
......@@ -301,8 +301,8 @@ &spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
dmas = <&edma 16
&edma 17>;
dmas = <&edma 16 0
&edma 17 0>;
dma-names = "tx0", "rx0";
flash: w25q64cvzpig@0 {
......
arch/arm/boot/dts/dm814x.dtsi
View file @ 7cd4a5eb
......@@ -75,6 +75,7 @@ usb0_phy: usb-phy@47401300 {
reg = <0x47401300 0x100>;
reg-names = "phy";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
......
arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts
View file @ 7cd4a5eb
......@@ -72,7 +72,8 @@ &charger {
};
&gpmc {
ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */
ethernet@gpmc {
pinctrl-names = "default";
......
arch/arm/boot/dts/logicpd-som-lv.dtsi
View file @ 7cd4a5eb
......@@ -33,11 +33,12 @@ wl12xx_vmmc: wl12xx_vmmc {
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
#phy-cells = <0>;
};
};
&gpmc {
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
......@@ -121,7 +122,7 @@ &i2c3 {
&mmc3 {
interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
pinctrl-0 = <&mmc3_pins>;
pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
pinctrl-names = "default";
vmmc-supply = <&wl12xx_vmmc>;
non-removable;
......@@ -132,8 +133,8 @@ &mmc3 {
wlcore: wlcore@2 {
compatible = "ti,wl1273";
reg = <2>;
interrupt-parent = <&gpio5>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
ref-clock-frequency = <26000000>;
};
};
......@@ -157,8 +158,6 @@ OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_da
OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
>;
......@@ -228,6 +227,12 @@ hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
>;
};
wl127x_gpio: pinmux_wl127x_gpio_pin {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
};
&omap3_pmx_core2 {
......
arch/arm/boot/dts/omap3-beagle-xm.dts
View file @ 7cd4a5eb
......@@ -90,6 +90,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
tfp410: encoder0 {
......
arch/arm/boot/dts/omap3-beagle.dts
View file @ 7cd4a5eb
......@@ -64,6 +64,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
sound {
......
arch/arm/boot/dts/omap3-cm-t3x.dtsi
View file @ 7cd4a5eb
......@@ -43,12 +43,14 @@ hsusb2_power: hsusb2_power_reg {
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&hsusb1_power>;
#phy-cells = <0>;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
ads7846reg: ads7846-reg {
......
arch/arm/boot/dts/omap3-evm-common.dtsi
View file @ 7cd4a5eb
......@@ -29,6 +29,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
leds {
......
arch/arm/boot/dts/omap3-gta04.dtsi
View file @ 7cd4a5eb
......@@ -120,6 +120,7 @@ pwm11: dmtimer-pwm {
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
#phy-cells = <0>;
};
tv0: connector {
......
arch/arm/boot/dts/omap3-igep0020-common.dtsi
View file @ 7cd4a5eb
......@@ -58,6 +58,7 @@ hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
vcc-supply = <&hsusb1_power>;
#phy-cells = <0>;
};
tfp410: encoder {
......
arch/arm/boot/dts/omap3-igep0030-common.dtsi
View file @ 7cd4a5eb
......@@ -37,6 +37,7 @@ user2 {
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
#phy-cells = <0>;
};
};
......
arch/arm/boot/dts/omap3-lilly-a83x.dtsi
View file @ 7cd4a5eb
......@@ -51,6 +51,7 @@ reg_vcc3: vcc3 {
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_vcc3>;
#phy-cells = <0>;
};
};
......
arch/arm/boot/dts/omap3-overo-base.dtsi
View file @ 7cd4a5eb
......@@ -51,6 +51,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
/* Regulator to trigger the nPoweron signal of the Wifi module */
......
arch/arm/boot/dts/omap3-pandora-common.dtsi
View file @ 7cd4a5eb
......@@ -205,6 +205,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* GPIO_16 */
vcc-supply = <&vaux2>;
#phy-cells = <0>;
};
/* HS USB Host VBUS supply
......
arch/arm/boot/dts/omap3-tao3530.dtsi
View file @ 7cd4a5eb
......@@ -46,6 +46,7 @@ hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */
vcc-supply = <&hsusb2_power>;
#phy-cells = <0>;
};
sound {
......
arch/arm/boot/dts/omap3.dtsi
View file @ 7cd4a5eb
......@@ -715,6 +715,7 @@ usbhsohci: ohci@48064400 {
compatible = "ti,ohci-omap3";
reg = <0x48064400 0x400>;
interrupts = <76>;
remote-wakeup-connected;
};
usbhsehci: ehci@48064800 {
......
arch/arm/boot/dts/omap4-droid4-xt894.dts
View file @ 7cd4a5eb
......@@ -73,6 +73,7 @@ hdmi_regulator: regulator-hdmi {
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
/* LCD regulator from sw5 source */
......
arch/arm/boot/dts/omap4-duovero.dtsi
View file @ 7cd4a5eb
......@@ -43,6 +43,7 @@ sound {
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
#phy-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hsusb1phy_pins>;
......
arch/arm/boot/dts/omap4-panda-common.dtsi
View file @ 7cd4a5eb
......@@ -89,6 +89,7 @@ hsusb1_power: hsusb1_power_reg {
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
#phy-cells = <0>;
vcc-supply = <&hsusb1_power>;
clocks = <&auxclk3_ck>;
clock-names = "main_clk";
......
arch/arm/boot/dts/omap4-var-som-om44.dtsi
View file @ 7cd4a5eb
......@@ -44,6 +44,7 @@ &hsusbb1_phy_rst_pins
reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */
vcc-supply = <&vbat>;
#phy-cells = <0>;
clocks = <&auxclk3_ck>;
clock-names = "main_clk";
......
arch/arm/boot/dts/omap4.dtsi
View file @ 7cd4a5eb
......@@ -1081,14 +1081,13 @@ usbhshost: usbhshost@4a064000 {
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3";
reg = <0x4a064800 0x400>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
remote-wakeup-connected;
};
usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap";
reg = <0x4a064c00 0x400>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
};
......
arch/arm/boot/dts/omap5-board-common.dtsi
View file @ 7cd4a5eb
......@@ -73,12 +73,14 @@ hsusb2_phy: hsusb2_phy {
clocks = <&auxclk1_ck>;
clock-names = "main_clk";
clock-frequency = <19200000>;
#phy-cells = <0>;
};
/* HS USB Host PHY on PORT 3 */
hsusb3_phy: hsusb3_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
#phy-cells = <0>;
};
tpd12s015: encoder {
......
arch/arm/boot/dts/omap5-cm-t54.dts
View file @ 7cd4a5eb
......@@ -63,12 +63,14 @@ ads7846reg: ads7846-reg {
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */
#phy-cells = <0>;
};
/* HS USB Host PHY on PORT 3 */
hsusb3_phy: hsusb3_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */
#phy-cells = <0>;
};
leds {
......
arch/arm/boot/dts/omap5.dtsi
View file @ 7cd4a5eb
......@@ -940,6 +940,7 @@ usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3";
reg = <0x4a064800 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
remote-wakeup-connected;
};
usbhsehci: ehci@4a064c00 {
......
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