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Commit 7d22bc45 authored by David S. Miller's avatar David S. Miller
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Merge branch 'net-phy-mscc-multiple-improvements' 

Antoine Tenart says:

====================
net: phy: mscc: multiple improvements

This series contains various improvements to the MSCC PHY driver, fixing
sparse and smatch warnings, using functions provided by the PHY core,
and improving the driver consistency and maintenance.

I don't think any of those improvements and fixes is worth backporting
to stable trees.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d0a45b5c b4368d2b
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Showing with 45 additions and 36 deletions
drivers/net/phy/mscc/mscc_macsec.c
View file @ 7d22bc45
......@@ -385,21 +385,23 @@ static void vsc8584_macsec_flow(struct phy_device *phydev,
}
if (bank == MACSEC_INGR && flow->match.sci && flow->rx_sa->sc->sci) {
u64 sci = (__force u64)flow->rx_sa->sc->sci;
match |= MSCC_MS_SAM_MISC_MATCH_TCI(BIT(3));
mask |= MSCC_MS_SAM_MASK_TCI_MASK(BIT(3)) |
MSCC_MS_SAM_MASK_SCI_MASK;
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_LO(idx),
lower_32_bits(flow->rx_sa->sc->sci));
lower_32_bits(sci));
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MATCH_SCI_HI(idx),
upper_32_bits(flow->rx_sa->sc->sci));
upper_32_bits(sci));
}
if (flow->match.etype) {
mask |= MSCC_MS_SAM_MASK_MAC_ETYPE_MASK;
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_SAM_MAC_SA_MATCH_HI(idx),
MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE(htons(flow->etype)));
MSCC_MS_SAM_MAC_SA_MATCH_HI_ETYPE((__force u32)htons(flow->etype)));
}
match |= MSCC_MS_SAM_MISC_MATCH_PRIORITY(flow->priority);
......@@ -545,7 +547,7 @@ static int vsc8584_macsec_transformation(struct phy_device *phydev,
int i, ret, index = flow->index;
u32 rec = 0, control = 0;
u8 hkey[16];
sci_t sci;
u64 sci;
ret = vsc8584_macsec_derive_key(flow->key, priv->secy->key_len, hkey);
if (ret)
......@@ -603,7 +605,7 @@ static int vsc8584_macsec_transformation(struct phy_device *phydev,
priv->secy->replay_window);
/* Set the input vectors */
sci = bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci;
sci = (__force u64)(bank == MACSEC_INGR ? flow->rx_sa->sc->sci : priv->secy->sci);
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
lower_32_bits(sci));
vsc8584_macsec_phy_write(phydev, bank, MSCC_MS_XFORM_REC(index, rec++),
......
drivers/net/phy/mscc/mscc_main.c
View file @ 7d22bc45
......@@ -1288,7 +1288,7 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
struct vsc8531_private *vsc8531 = phydev->priv;
u16 val, addr;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
......@@ -1297,7 +1297,7 @@ static void vsc8584_get_base_addr(struct phy_device *phydev)
val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
__phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
/* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
* PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
......@@ -1331,7 +1331,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
......@@ -1375,8 +1375,10 @@ static int vsc8584_config_init(struct phy_device *phydev)
goto err;
}
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXTENDED_GPIO);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXTENDED_GPIO);
if (ret)
goto err;
val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
val &= ~MAC_CFG_MASK;
......@@ -1395,6 +1397,11 @@ static int vsc8584_config_init(struct phy_device *phydev)
if (ret)
goto err;
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STANDARD);
if (ret)
goto err;
if (!phy_interface_is_rgmii(phydev)) {
val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
PROC_CMD_READ_MOD_WRITE_PORT;
......@@ -1428,7 +1435,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
if (ret)
goto err;
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
ret = vsc8584_macsec_init(phydev);
if (ret)
......@@ -1436,9 +1443,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
ret = vsc8584_ptp_init(phydev);
if (ret)
goto err;
phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
return ret;
val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
......@@ -1469,7 +1474,7 @@ static int vsc8584_config_init(struct phy_device *phydev)
return 0;
err:
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return ret;
}
......@@ -1755,7 +1760,7 @@ static int vsc8514_config_init(struct phy_device *phydev)
phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* Some parts of the init sequence are identical for every PHY in the
* package. Some parts are modifying the GPIO register bank which is a
......@@ -1771,15 +1776,21 @@ static int vsc8514_config_init(struct phy_device *phydev)
if (phy_package_init_once(phydev))
vsc8514_config_pre_init(phydev);
phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXTENDED_GPIO);
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_EXTENDED_GPIO);
if (ret)
goto err;
val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
val &= ~MAC_CFG_MASK;
val |= MAC_CFG_QSGMII;
ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
if (ret)
goto err;
ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STANDARD);
if (ret)
goto err;
......@@ -1843,14 +1854,14 @@ static int vsc8514_config_init(struct phy_device *phydev)
reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
PHY_S6G_PLL_STATUS);
if (reg == 0xffffffff) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -EIO;
}
} while (time_before(jiffies, deadline) && (reg & BIT(12)));
if (reg & BIT(12)) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -ETIMEDOUT;
}
......@@ -1870,23 +1881,18 @@ static int vsc8514_config_init(struct phy_device *phydev)
reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET,
PHY_S6G_IB_STATUS0);
if (reg == 0xffffffff) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -EIO;
}
} while (time_before(jiffies, deadline) && !(reg & BIT(8)));
if (!(reg & BIT(8))) {
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return -ETIMEDOUT;
}
mutex_unlock(&phydev->mdio.bus->mdio_lock);
ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
if (ret)
return ret;
phy_unlock_mdio_bus(phydev);
ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
......@@ -1908,7 +1914,7 @@ static int vsc8514_config_init(struct phy_device *phydev)
return ret;
err:
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return ret;
}
......
drivers/net/phy/mscc/mscc_ptp.c
View file @ 7d22bc45
......@@ -75,11 +75,12 @@ static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
blk_hw = base_port ? EGRESS_ENGINE_0 : EGRESS_ENGINE_1;
break;
case PROCESSOR:
default:
blk_hw = base_port ? PROCESSOR_0 : PROCESSOR_1;
break;
}
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_1588);
......@@ -97,7 +98,7 @@ static u32 vsc85xx_ts_read_csr(struct phy_device *phydev, enum ts_blk blk,
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
return val;
}
......@@ -129,7 +130,7 @@ static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
break;
}
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
bypass = phy_ts_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
......@@ -153,7 +154,7 @@ static void vsc85xx_ts_write_csr(struct phy_device *phydev, enum ts_blk blk,
if (cond && upper)
phy_ts_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, bypass);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
}
/* Pick bytes from PTP header */
......@@ -1272,7 +1273,7 @@ static int __vsc8584_init_ptp(struct phy_device *phydev)
u32 val;
if (!vsc8584_is_1588_input_clk_configured(phydev)) {
mutex_lock(&phydev->mdio.bus->mdio_lock);
phy_lock_mdio_bus(phydev);
/* 1588_DIFF_INPUT_CLK configuration: Use an external clock for
* the LTC, as per 3.13.29 in the VSC8584 datasheet.
......@@ -1284,7 +1285,7 @@ static int __vsc8584_init_ptp(struct phy_device *phydev)
phy_ts_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
MSCC_PHY_PAGE_STANDARD);
mutex_unlock(&phydev->mdio.bus->mdio_lock);
phy_unlock_mdio_bus(phydev);
vsc8584_set_input_clk_configured(phydev);
}
......@@ -1563,7 +1564,7 @@ int vsc8584_ptp_probe(struct phy_device *phydev)
/* Retrieve the shared load/save GPIO. Request it as non exclusive as
* the same GPIO can be requested by all the PHYs of the same package.
* Ths GPIO must be used with the gpio_lock taken (the lock is shared
* This GPIO must be used with the gpio_lock taken (the lock is shared
* between all PHYs).
*/
vsc8531->load_save = devm_gpiod_get_optional(&phydev->mdio.dev, "load-save",
......
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