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Commit 7d9a39e0 authored by Rylan Dmello's avatar Rylan Dmello Committed by Greg Kroah-Hartman
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staging: qlge: Fix indentation in ql_set_mac_addr_reg 

Based on Joe Perches' feedback, fix the indentation throughout
ql_set_mac_addr_reg. This helps fix several "line over 80 characters"
warnings along with the original "multiple line dereference" warning.

Fix checkpatch.pl warnings:

  WARNING: Avoid multiple line dereference - prefer 'qdev->func'
  WARNING: line over 80 characters
Signed-off-by: default avatarRylan Dmello <mail@rylan.coffee>
Link: https://lore.kernel.org/r/299f2cb3b7d4efa30b44d4d1defbcd5f54bd7eaf.1588209862.git.mail@rylan.coffeeSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent e3881eb5
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Showing with 78 additions and 89 deletions
drivers/staging/qlge/qlge_main.c
View file @ 7d9a39e0
...@@ -329,100 +329,89 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type, ...@@ -329,100 +329,89 @@ static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
int status = 0; int status = 0;
switch (type) { switch (type) {
case MAC_ADDR_TYPE_MULTI_MAC: case MAC_ADDR_TYPE_MULTI_MAC: {
{ u32 upper = (addr[0] << 8) | addr[1];
u32 upper = (addr[0] << 8) | addr[1]; u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[5]);
(addr[4] << 8) | (addr[5]);
status = status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_wait_reg_rdy(qdev, if (status)
MAC_ADDR_IDX, MAC_ADDR_MW, 0); goto exit;
if (status) ql_write32(qdev, MAC_ADDR_IDX,
goto exit; (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type |
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | MAC_ADDR_E);
(index << MAC_ADDR_IDX_SHIFT) | ql_write32(qdev, MAC_ADDR_DATA, lower);
type | MAC_ADDR_E); status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_write32(qdev, MAC_ADDR_DATA, lower); if (status)
status = goto exit;
ql_wait_reg_rdy(qdev, ql_write32(qdev, MAC_ADDR_IDX,
MAC_ADDR_IDX, MAC_ADDR_MW, 0); (offset++) | (index << MAC_ADDR_IDX_SHIFT) | type |
if (status) MAC_ADDR_E);
goto exit;
ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
(index << MAC_ADDR_IDX_SHIFT) |
type | MAC_ADDR_E);
ql_write32(qdev, MAC_ADDR_DATA, upper); ql_write32(qdev, MAC_ADDR_DATA, upper);
status = status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_wait_reg_rdy(qdev, if (status)
MAC_ADDR_IDX, MAC_ADDR_MW, 0); goto exit;
if (status) break;
goto exit; }
break; case MAC_ADDR_TYPE_CAM_MAC: {
} u32 cam_output;
case MAC_ADDR_TYPE_CAM_MAC: u32 upper = (addr[0] << 8) | addr[1];
{ u32 lower = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
u32 cam_output;
u32 upper = (addr[0] << 8) | addr[1];
u32 lower =
(addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
(addr[5]); (addr[5]);
status = status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status)
if (status) goto exit;
goto exit; ql_write32(qdev, MAC_ADDR_IDX,
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ (offset++) | /* offset */
(index << MAC_ADDR_IDX_SHIFT) | /* index */ (index << MAC_ADDR_IDX_SHIFT) | /* index */
type); /* type */ type); /* type */
ql_write32(qdev, MAC_ADDR_DATA, lower); ql_write32(qdev, MAC_ADDR_DATA, lower);
status = status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status)
if (status) goto exit;
goto exit; ql_write32(qdev, MAC_ADDR_IDX,
ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */ (offset++) | /* offset */
(index << MAC_ADDR_IDX_SHIFT) | /* index */ (index << MAC_ADDR_IDX_SHIFT) | /* index */
type); /* type */ type); /* type */
ql_write32(qdev, MAC_ADDR_DATA, upper); ql_write32(qdev, MAC_ADDR_DATA, upper);
status = status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); if (status)
if (status) goto exit;
goto exit; ql_write32(qdev, MAC_ADDR_IDX,
ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */ (offset) | /* offset */
(index << MAC_ADDR_IDX_SHIFT) | /* index */ (index << MAC_ADDR_IDX_SHIFT) | /* index */
type); /* type */ type); /* type */
/* This field should also include the queue id /* This field should also include the queue id
* and possibly the function id. Right now we hardcode * and possibly the function id. Right now we hardcode
* the route field to NIC core. * the route field to NIC core.
*/ */
cam_output = (CAM_OUT_ROUTE_NIC | cam_output = (CAM_OUT_ROUTE_NIC |
(qdev-> (qdev->func << CAM_OUT_FUNC_SHIFT) |
func << CAM_OUT_FUNC_SHIFT) | (0 << CAM_OUT_CQ_ID_SHIFT));
(0 << CAM_OUT_CQ_ID_SHIFT)); if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX) cam_output |= CAM_OUT_RV;
cam_output |= CAM_OUT_RV; /* route to NIC core */
/* route to NIC core */ ql_write32(qdev, MAC_ADDR_DATA, cam_output);
ql_write32(qdev, MAC_ADDR_DATA, cam_output); break;
break; }
} case MAC_ADDR_TYPE_VLAN: {
case MAC_ADDR_TYPE_VLAN: u32 enable_bit = *((u32 *)&addr[0]);
{ /* For VLAN, the addr actually holds a bit that
u32 enable_bit = *((u32 *) &addr[0]); * either enables or disables the vlan id we are
/* For VLAN, the addr actually holds a bit that * addressing. It's either MAC_ADDR_E on or off.
* either enables or disables the vlan id we are * That's bit-27 we're talking about.
* addressing. It's either MAC_ADDR_E on or off. */
* That's bit-27 we're talking about. status = ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0);
*/ if (status)
status = goto exit;
ql_wait_reg_rdy(qdev, MAC_ADDR_IDX, MAC_ADDR_MW, 0); ql_write32(qdev, MAC_ADDR_IDX,
if (status) offset | /* offset */
goto exit; (index << MAC_ADDR_IDX_SHIFT) | /* index */
ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */ type | /* type */
(index << MAC_ADDR_IDX_SHIFT) | /* index */ enable_bit); /* enable/disable */
type | /* type */ break;
enable_bit); /* enable/disable */ }
break;
}
case MAC_ADDR_TYPE_MULTI_FLTR: case MAC_ADDR_TYPE_MULTI_FLTR:
default: default:
netif_crit(qdev, ifup, qdev->ndev, netif_crit(qdev, ifup, qdev->ndev,
......
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