Commit 7f6e7186 authored by Nikola Cornij's avatar Nikola Cornij Committed by Alex Deucher

drm/amd/display: Zero-out dsc init regs

[why]
Before a statically allocated PPS data structure, that did
get zeroed-out at startup, had been re-used for making packed PPS
SDP. With S3 fix, using a non-initialized PPS data structure was
introduced, while wrongly assuming it'd get initialized before it's
populated. As a consequence 'vbr_enable' and perhaps some other
fields are left uninitialized when making packed PPS SDP. This can
affect 'simple_422' as well because of the way PPS SDP packing is
done (the fields are not masked first, only shifted). The behavior
will be different, depending on the content of uninitialized data.

[how]
Zero-out PPS data structure at initialization time before it's
populated

Fixes: 1a9e3d45 ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end")
Signed-off-by: default avatarNikola Cornij <nikola.cornij@amd.com>
Reviewed-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 387ad34c
...@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) ...@@ -447,6 +447,8 @@ static void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
{ {
int i; int i;
memset(reg_vals, 0, sizeof(struct dsc_reg_values));
/* Non-PPS values */ /* Non-PPS values */
reg_vals->dsc_clock_enable = 1; reg_vals->dsc_clock_enable = 1;
reg_vals->dsc_clock_gating_disable = 0; reg_vals->dsc_clock_gating_disable = 0;
......
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