Commit 8000bc3f authored by Duc Dang's avatar Duc Dang

arm64: dts: Add L2 cache topology for APM X-Gene SoC

In APM X-Gene SoC (both v1 and v2), each pair of processors
shares the same L2 cache. This patch adds l2-cache entries into
X-Gene SoC device tree to demonstrate this configuration.
Signed-off-by: default avatarDuc Dang <dhdang@apm.com>
parent 79402f35
...@@ -25,6 +25,7 @@ cpu@000 { ...@@ -25,6 +25,7 @@ cpu@000 {
reg = <0x0 0x000>; reg = <0x0 0x000>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
}; };
cpu@001 { cpu@001 {
device_type = "cpu"; device_type = "cpu";
...@@ -32,6 +33,7 @@ cpu@001 { ...@@ -32,6 +33,7 @@ cpu@001 {
reg = <0x0 0x001>; reg = <0x0 0x001>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
}; };
cpu@100 { cpu@100 {
device_type = "cpu"; device_type = "cpu";
...@@ -39,6 +41,7 @@ cpu@100 { ...@@ -39,6 +41,7 @@ cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
}; };
cpu@101 { cpu@101 {
device_type = "cpu"; device_type = "cpu";
...@@ -46,6 +49,7 @@ cpu@101 { ...@@ -46,6 +49,7 @@ cpu@101 {
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
}; };
cpu@200 { cpu@200 {
device_type = "cpu"; device_type = "cpu";
...@@ -53,6 +57,7 @@ cpu@200 { ...@@ -53,6 +57,7 @@ cpu@200 {
reg = <0x0 0x200>; reg = <0x0 0x200>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
}; };
cpu@201 { cpu@201 {
device_type = "cpu"; device_type = "cpu";
...@@ -60,6 +65,7 @@ cpu@201 { ...@@ -60,6 +65,7 @@ cpu@201 {
reg = <0x0 0x201>; reg = <0x0 0x201>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
}; };
cpu@300 { cpu@300 {
device_type = "cpu"; device_type = "cpu";
...@@ -67,6 +73,7 @@ cpu@300 { ...@@ -67,6 +73,7 @@ cpu@300 {
reg = <0x0 0x300>; reg = <0x0 0x300>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
}; };
cpu@301 { cpu@301 {
device_type = "cpu"; device_type = "cpu";
...@@ -74,6 +81,19 @@ cpu@301 { ...@@ -74,6 +81,19 @@ cpu@301 {
reg = <0x0 0x301>; reg = <0x0 0x301>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
}; };
}; };
......
...@@ -25,6 +25,7 @@ cpu@000 { ...@@ -25,6 +25,7 @@ cpu@000 {
reg = <0x0 0x000>; reg = <0x0 0x000>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
}; };
cpu@001 { cpu@001 {
device_type = "cpu"; device_type = "cpu";
...@@ -32,6 +33,7 @@ cpu@001 { ...@@ -32,6 +33,7 @@ cpu@001 {
reg = <0x0 0x001>; reg = <0x0 0x001>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
}; };
cpu@100 { cpu@100 {
device_type = "cpu"; device_type = "cpu";
...@@ -39,6 +41,7 @@ cpu@100 { ...@@ -39,6 +41,7 @@ cpu@100 {
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
}; };
cpu@101 { cpu@101 {
device_type = "cpu"; device_type = "cpu";
...@@ -46,6 +49,7 @@ cpu@101 { ...@@ -46,6 +49,7 @@ cpu@101 {
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
}; };
cpu@200 { cpu@200 {
device_type = "cpu"; device_type = "cpu";
...@@ -53,6 +57,7 @@ cpu@200 { ...@@ -53,6 +57,7 @@ cpu@200 {
reg = <0x0 0x200>; reg = <0x0 0x200>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
}; };
cpu@201 { cpu@201 {
device_type = "cpu"; device_type = "cpu";
...@@ -60,6 +65,7 @@ cpu@201 { ...@@ -60,6 +65,7 @@ cpu@201 {
reg = <0x0 0x201>; reg = <0x0 0x201>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
}; };
cpu@300 { cpu@300 {
device_type = "cpu"; device_type = "cpu";
...@@ -67,6 +73,7 @@ cpu@300 { ...@@ -67,6 +73,7 @@ cpu@300 {
reg = <0x0 0x300>; reg = <0x0 0x300>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
}; };
cpu@301 { cpu@301 {
device_type = "cpu"; device_type = "cpu";
...@@ -74,6 +81,19 @@ cpu@301 { ...@@ -74,6 +81,19 @@ cpu@301 {
reg = <0x0 0x301>; reg = <0x0 0x301>;
enable-method = "spin-table"; enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>; cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
}; };
}; };
......
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