Commit 84dd0f78 authored by Naveen N. Rao's avatar Naveen N. Rao Committed by Kamal Mostafa

perf tools: Fix perf regs mask generation

commit f4782207 upstream.

On some architectures (powerpc in particular), the number of registers
exceeds what can be represented in an integer bitmask. Ensure we
generate the proper bitmask on such platforms.

Fixes: 71ad0f5e ("perf tools: Support for DWARF CFI unwinding on post processing")
Signed-off-by: default avatarNaveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Acked-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarKamal Mostafa <kamal@canonical.com>
parent 25e2014c
......@@ -7,18 +7,18 @@ int perf_reg_value(u64 *valp, struct regs_dump *regs, int id)
int i, idx = 0;
u64 mask = regs->mask;
if (regs->cache_mask & (1 << id))
if (regs->cache_mask & (1ULL << id))
goto out;
if (!(mask & (1 << id)))
if (!(mask & (1ULL << id)))
return -EINVAL;
for (i = 0; i < id; i++) {
if (mask & (1 << i))
if (mask & (1ULL << i))
idx++;
}
regs->cache_mask |= (1 << id);
regs->cache_mask |= (1ULL << id);
regs->cache_regs[id] = regs->regs[idx];
out:
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment