Commit 85323a99 authored by Ian Campbell's avatar Ian Campbell Committed by Konrad Rzeszutek Wilk

xen: arm: mandate EABI and use generic atomic operations.

Rob Herring has observed that c81611c4 "xen: event channel arrays are
xen_ulong_t and not unsigned long" introduced a compile failure when building
without CONFIG_AEABI:

/tmp/ccJaIZOW.s: Assembler messages:
/tmp/ccJaIZOW.s:831: Error: even register required -- `ldrexd r5,r6,[r4]'

Will Deacon pointed out that this is because OABI does not require even base
registers for 64-bit values. We can avoid this by simply using the existing
atomic64_xchg operation and the same containerof trick as used by the cmpxchg
macros. However since this code is used on memory which is shared with the
hypervisor we require proper atomic instructions and cannot use the generic
atomic64 callbacks (which are based on spinlocks), therefore add a dependency
on !GENERIC_ATOMIC64. Since we already depend on !CPU_V6 there isn't much
downside to this.

While thinking about this we also observed that OABI has different struct
alignment requirements to EABI, which is a problem for hypercall argument
structs which are shared with the hypervisor and which must be in EABI layout.
Since I don't expect people to want to run OABI kernels on Xen depend on
CONFIG_AEABI explicitly too (although it also happens to be enforced by the
!GENERIC_ATOMIC64 requirement too).
Signed-off-by: default avatarIan Campbell <ian.campbell@citrix.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robherring2@gmail.com>
Acked-by: default avatarStefano Stabellini <Stefano.Stabellini@eu.citrix.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
parent c705c78c
...@@ -1866,8 +1866,9 @@ config XEN_DOM0 ...@@ -1866,8 +1866,9 @@ config XEN_DOM0
config XEN config XEN
bool "Xen guest support on ARM (EXPERIMENTAL)" bool "Xen guest support on ARM (EXPERIMENTAL)"
depends on ARM && OF depends on ARM && AEABI && OF
depends on CPU_V7 && !CPU_V6 depends on CPU_V7 && !CPU_V6
depends on !GENERIC_ATOMIC64
help help
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
......
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
#define _ASM_ARM_XEN_EVENTS_H #define _ASM_ARM_XEN_EVENTS_H
#include <asm/ptrace.h> #include <asm/ptrace.h>
#include <asm/atomic.h>
enum ipi_vector { enum ipi_vector {
XEN_PLACEHOLDER_VECTOR, XEN_PLACEHOLDER_VECTOR,
...@@ -15,26 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs) ...@@ -15,26 +16,8 @@ static inline int xen_irqs_disabled(struct pt_regs *regs)
return raw_irqs_disabled_flags(regs->ARM_cpsr); return raw_irqs_disabled_flags(regs->ARM_cpsr);
} }
/* #define xchg_xen_ulong(ptr, val) atomic64_xchg(container_of((ptr), \
* We cannot use xchg because it does not support 8-byte atomic64_t, \
* values. However it is safe to use {ldr,dtd}exd directly because all counter), (val))
* platforms which Xen can run on support those instructions.
*/
static inline xen_ulong_t xchg_xen_ulong(xen_ulong_t *ptr, xen_ulong_t val)
{
xen_ulong_t oldval;
unsigned int tmp;
wmb();
asm volatile("@ xchg_xen_ulong\n"
"1: ldrexd %0, %H0, [%3]\n"
" strexd %1, %2, %H2, [%3]\n"
" teq %1, #0\n"
" bne 1b"
: "=&r" (oldval), "=&r" (tmp)
: "r" (val), "r" (ptr)
: "memory", "cc");
return oldval;
}
#endif /* _ASM_ARM_XEN_EVENTS_H */ #endif /* _ASM_ARM_XEN_EVENTS_H */
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