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Commit 8644cdf9 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
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[media] omap3isp: Replace many MMIO regions by two 

The omap3isp MMIO register block is contiguous in the MMIO register space
apart from the fact that the ISP IOMMU register block is in the middle of
the area. Ioremap it at two occasions, and keep the rest of the layout of
the register space internal to the omap3isp driver.
Signed-off-by: default avatarSakari Ailus <sakari.ailus@iki.fi>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent 503596a1
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Showing with 66 additions and 153 deletions
arch/arm/mach-omap2/devices.c
View file @ 8644cdf9
...@@ -74,72 +74,12 @@ omap_postcore_initcall(omap3_l3_init); ...@@ -74,72 +74,12 @@ omap_postcore_initcall(omap3_l3_init);
static struct resource omap3isp_resources[] = { static struct resource omap3isp_resources[] = {
{ {
.start = OMAP3430_ISP_BASE, .start = OMAP3430_ISP_BASE,
.end = OMAP3430_ISP_END, .end = OMAP3430_ISP_BASE + 0x12fc,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
.start = OMAP3430_ISP_CCP2_BASE, .start = OMAP3430_ISP_BASE2,
.end = OMAP3430_ISP_CCP2_END, .end = OMAP3430_ISP_BASE2 + 0x0600,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_CCDC_BASE,
.end = OMAP3430_ISP_CCDC_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_HIST_BASE,
.end = OMAP3430_ISP_HIST_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_H3A_BASE,
.end = OMAP3430_ISP_H3A_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_PREV_BASE,
.end = OMAP3430_ISP_PREV_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_RESZ_BASE,
.end = OMAP3430_ISP_RESZ_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_SBL_BASE,
.end = OMAP3430_ISP_SBL_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_CSI2A_REGS1_BASE,
.end = OMAP3430_ISP_CSI2A_REGS1_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_CSIPHY2_BASE,
.end = OMAP3430_ISP_CSIPHY2_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3630_ISP_CSI2A_REGS2_BASE,
.end = OMAP3630_ISP_CSI2A_REGS2_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3630_ISP_CSI2C_REGS1_BASE,
.end = OMAP3630_ISP_CSI2C_REGS1_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3630_ISP_CSIPHY1_BASE,
.end = OMAP3630_ISP_CSIPHY1_END,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3630_ISP_CSI2C_REGS2_BASE,
.end = OMAP3630_ISP_CSI2C_REGS2_END,
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
{ {
......
arch/arm/mach-omap2/omap34xx.h
View file @ 8644cdf9
...@@ -46,39 +46,9 @@ ...@@ -46,39 +46,9 @@
#define OMAP34XX_IC_BASE 0x48200000 #define OMAP34XX_IC_BASE 0x48200000
#define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000)
#define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
#define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) #define OMAP3430_ISP_BASE2 (OMAP3430_ISP_BASE + 0x1800)
#define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600)
#define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00)
#define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00)
#define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00)
#define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000)
#define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200)
#define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400)
#define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800)
#define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970)
#define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0)
#define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00)
#define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70)
#define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0)
#define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F)
#define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077)
#define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF)
#define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7)
#define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047)
#define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F)
#define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F)
#define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB)
#define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB)
#define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F)
#define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F)
#define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B)
#define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F)
#define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F)
#define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B)
#define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F)
#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
......
drivers/media/platform/omap3isp/isp.c
View file @ 8644cdf9
...@@ -86,35 +86,43 @@ static void isp_restore_ctx(struct isp_device *isp); ...@@ -86,35 +86,43 @@ static void isp_restore_ctx(struct isp_device *isp);
static const struct isp_res_mapping isp_res_maps[] = { static const struct isp_res_mapping isp_res_maps[] = {
{ {
.isp_rev = ISP_REVISION_2_0, .isp_rev = ISP_REVISION_2_0,
.map = 1 << OMAP3_ISP_IOMEM_MAIN | .offset = {
1 << OMAP3_ISP_IOMEM_CCP2 | /* first MMIO area */
1 << OMAP3_ISP_IOMEM_CCDC | 0x0000, /* base, len 0x0070 */
1 << OMAP3_ISP_IOMEM_HIST | 0x0400, /* ccp2, len 0x01f0 */
1 << OMAP3_ISP_IOMEM_H3A | 0x0600, /* ccdc, len 0x00a8 */
1 << OMAP3_ISP_IOMEM_PREV | 0x0a00, /* hist, len 0x0048 */
1 << OMAP3_ISP_IOMEM_RESZ | 0x0c00, /* h3a, len 0x0060 */
1 << OMAP3_ISP_IOMEM_SBL | 0x0e00, /* preview, len 0x00a0 */
1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 | 0x1000, /* resizer, len 0x00ac */
1 << OMAP3_ISP_IOMEM_CSIPHY2, 0x1200, /* sbl, len 0x00fc */
/* second MMIO area */
0x0000, /* csi2a, len 0x0170 */
0x0170, /* csiphy2, len 0x000c */
},
.syscon_offset = 0xdc, .syscon_offset = 0xdc,
.phy_type = ISP_PHY_TYPE_3430, .phy_type = ISP_PHY_TYPE_3430,
}, },
{ {
.isp_rev = ISP_REVISION_15_0, .isp_rev = ISP_REVISION_15_0,
.map = 1 << OMAP3_ISP_IOMEM_MAIN | .offset = {
1 << OMAP3_ISP_IOMEM_CCP2 | /* first MMIO area */
1 << OMAP3_ISP_IOMEM_CCDC | 0x0000, /* base, len 0x0070 */
1 << OMAP3_ISP_IOMEM_HIST | 0x0400, /* ccp2, len 0x01f0 */
1 << OMAP3_ISP_IOMEM_H3A | 0x0600, /* ccdc, len 0x00a8 */
1 << OMAP3_ISP_IOMEM_PREV | 0x0a00, /* hist, len 0x0048 */
1 << OMAP3_ISP_IOMEM_RESZ | 0x0c00, /* h3a, len 0x0060 */
1 << OMAP3_ISP_IOMEM_SBL | 0x0e00, /* preview, len 0x00a0 */
1 << OMAP3_ISP_IOMEM_CSI2A_REGS1 | 0x1000, /* resizer, len 0x00ac */
1 << OMAP3_ISP_IOMEM_CSIPHY2 | 0x1200, /* sbl, len 0x00fc */
1 << OMAP3_ISP_IOMEM_CSI2A_REGS2 | /* second MMIO area */
1 << OMAP3_ISP_IOMEM_CSI2C_REGS1 | 0x0000, /* csi2a, len 0x0170 (1st area) */
1 << OMAP3_ISP_IOMEM_CSIPHY1 | 0x0170, /* csiphy2, len 0x000c */
1 << OMAP3_ISP_IOMEM_CSI2C_REGS2, 0x01c0, /* csi2a, len 0x0040 (2nd area) */
0x0400, /* csi2c, len 0x0170 (1st area) */
0x0570, /* csiphy1, len 0x000c */
0x05c0, /* csi2c, len 0x0040 (2nd area) */
},
.syscon_offset = 0x2f0, .syscon_offset = 0x2f0,
.phy_type = ISP_PHY_TYPE_3630, .phy_type = ISP_PHY_TYPE_3630,
}, },
...@@ -2235,27 +2243,6 @@ static int isp_remove(struct platform_device *pdev) ...@@ -2235,27 +2243,6 @@ static int isp_remove(struct platform_device *pdev)
return 0; return 0;
} }
static int isp_map_mem_resource(struct platform_device *pdev,
struct isp_device *isp,
enum isp_mem_resources res)
{
struct resource *mem;
/* request the mem region for the camera registers */
mem = platform_get_resource(pdev, IORESOURCE_MEM, res);
/* map the region */
isp->mmio_base[res] = devm_ioremap_resource(isp->dev, mem);
if (IS_ERR(isp->mmio_base[res]))
return PTR_ERR(isp->mmio_base[res]);
if (res == OMAP3_ISP_IOMEM_HIST)
isp->mmio_hist_base_phys = mem->start;
return 0;
}
/* /*
* isp_probe - Probe ISP platform device * isp_probe - Probe ISP platform device
* @pdev: Pointer to ISP platform device * @pdev: Pointer to ISP platform device
...@@ -2271,6 +2258,7 @@ static int isp_probe(struct platform_device *pdev) ...@@ -2271,6 +2258,7 @@ static int isp_probe(struct platform_device *pdev)
{ {
struct isp_platform_data *pdata = pdev->dev.platform_data; struct isp_platform_data *pdata = pdev->dev.platform_data;
struct isp_device *isp; struct isp_device *isp;
struct resource *mem;
int ret; int ret;
int i, m; int i, m;
...@@ -2303,10 +2291,21 @@ static int isp_probe(struct platform_device *pdev) ...@@ -2303,10 +2291,21 @@ static int isp_probe(struct platform_device *pdev)
* *
* The ISP clock tree is revision-dependent. We thus need to enable ICLK * The ISP clock tree is revision-dependent. We thus need to enable ICLK
* manually to read the revision before calling __omap3isp_get(). * manually to read the revision before calling __omap3isp_get().
*
* Start by mapping the ISP MMIO area, which is in two pieces.
* The ISP IOMMU is in between. Map both now, and fill in the
* ISP revision specific portions a little later in the
* function.
*/ */
ret = isp_map_mem_resource(pdev, isp, OMAP3_ISP_IOMEM_MAIN); for (i = 0; i < 2; i++) {
if (ret < 0) unsigned int map_idx = i ? OMAP3_ISP_IOMEM_CSI2A_REGS1 : 0;
goto error;
mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
isp->mmio_base[map_idx] =
devm_ioremap_resource(isp->dev, mem);
if (IS_ERR(isp->mmio_base[map_idx]))
return PTR_ERR(isp->mmio_base[map_idx]);
}
ret = isp_get_clocks(isp); ret = isp_get_clocks(isp);
if (ret < 0) if (ret < 0)
...@@ -2347,13 +2346,17 @@ static int isp_probe(struct platform_device *pdev) ...@@ -2347,13 +2346,17 @@ static int isp_probe(struct platform_device *pdev)
goto error_isp; goto error_isp;
} }
for (i = 1; i < OMAP3_ISP_IOMEM_LAST; i++) { for (i = 1; i < OMAP3_ISP_IOMEM_CSI2A_REGS1; i++)
if (isp_res_maps[m].map & 1 << i) { isp->mmio_base[i] =
ret = isp_map_mem_resource(pdev, isp, i); isp->mmio_base[0] + isp_res_maps[m].offset[i];
if (ret)
goto error_isp; for (i = OMAP3_ISP_IOMEM_CSIPHY2; i < OMAP3_ISP_IOMEM_LAST; i++)
} isp->mmio_base[i] =
} isp->mmio_base[OMAP3_ISP_IOMEM_CSI2A_REGS1]
+ isp_res_maps[m].offset[i];
isp->mmio_hist_base_phys =
mem->start + isp_res_maps[m].offset[OMAP3_ISP_IOMEM_HIST];
isp->syscon = syscon_regmap_lookup_by_pdevname("syscon.0"); isp->syscon = syscon_regmap_lookup_by_pdevname("syscon.0");
if (IS_ERR(isp->syscon)) { if (IS_ERR(isp->syscon)) {
......
drivers/media/platform/omap3isp/isp.h
View file @ 8644cdf9
...@@ -99,7 +99,7 @@ struct regmap; ...@@ -99,7 +99,7 @@ struct regmap;
/* /*
* struct isp_res_mapping - Map ISP io resources to ISP revision. * struct isp_res_mapping - Map ISP io resources to ISP revision.
* @isp_rev: ISP_REVISION_x_x * @isp_rev: ISP_REVISION_x_x
* @map: bitmap for enum isp_mem_resources * @offset: register offsets of various ISP sub-blocks
* @syscon_offset: offset of the syscon register for 343x / 3630 * @syscon_offset: offset of the syscon register for 343x / 3630
* (CONTROL_CSIRXFE / CONTROL_CAMERA_PHY_CTRL, respectively) * (CONTROL_CSIRXFE / CONTROL_CAMERA_PHY_CTRL, respectively)
* from the syscon base address * from the syscon base address
...@@ -107,7 +107,7 @@ struct regmap; ...@@ -107,7 +107,7 @@ struct regmap;
*/ */
struct isp_res_mapping { struct isp_res_mapping {
u32 isp_rev; u32 isp_rev;
u32 map; u32 offset[OMAP3_ISP_IOMEM_LAST];
u32 syscon_offset; u32 syscon_offset;
u32 phy_type; u32 phy_type;
}; };
......
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