Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (60 commits)
  [MIPS] Fulong doesn't need ISA DMA.
  [MIPS] IP27: intr_sconnect_level: don't disable interrupts.
  [MIPS] IP27: startup_bridge_irq: connect interrupt.
  [MIPS] IP27: shutdown_bridge_irq: don't free irq.
  [MIPS] Sort out handling of ISA-less PCI systems.
  [MIPS] Add __cmpdi2
  [MIPS] HOTPLUG: Make register_pci_controller __devinit.
  [MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus.
  [MIPS] PCI: Remove __devinit attribute from pcibios_fixup_bus.
  [MIPS] Delete duplicate inclusion of <linux/delay.h>.
  [MIPS] Polish <asm/edac.h>.
  [MIPS] IP22: Export sgi_gfxaddr for use by the Newport console driver.
  [MIPS] Maintain si_code field properly for FP exceptions
  [MIPS] SMTC: Fix duplicate status dumps on NMI
  [MIPS] Unconditionally writeback and invalidate caches on kexec.
  [PATCH] rtc: Make rtc-rs5c348 driver hotplug-aware
  [MIPS] Fix gcc 3.3 warning.
  [MIPS] Fix invalid semicolon after if statement
  [MIPS] Update Cobalt defconfig
  [MIPS] Update workpad_defconfig
  ...

arch/mips/Kconfig

@@ -28,7 +28,6 @@ config BASLER_EXCITE
 	select MIPS_RM9122
 	select SYS_HAS_CPU_RM9000
 	select SYS_SUPPORTS_32BIT_KERNEL
-	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_KGDB
 	help
@@ -126,6 +125,7 @@ config LEMOTE_FULONG
 	select SYS_SUPPORTS_HIGHMEM
 	select SYS_HAS_EARLY_PRINTK
 	select GENERIC_HARDIRQS_NO__DO_IRQ
+	select GENERIC_ISA_DMA_SUPPORT_BROKEN
 	select CPU_HAS_WB
 	help
 	  Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and
@@ -192,8 +192,7 @@ config MIPS_MALTA
 	  board.
 
 config MIPS_SEAD
-	bool "MIPS SEAD board (EXPERIMENTAL)"
-	depends on EXPERIMENTAL
+	bool "MIPS SEAD board"
 	select IRQ_CPU
 	select DMA_NONCOHERENT
 	select SYS_HAS_EARLY_PRINTK
@@ -528,6 +527,7 @@ config TOSHIBA_JMR3927
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
 	select MIPS_TX3927
+	select IRQ_TXX9
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX39XX
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -540,7 +540,9 @@ config TOSHIBA_RBTX4927
 	select DMA_NONCOHERENT
 	select HAS_TXX9_SERIAL
 	select HW_HAS_PCI
-	select I8259
+	select IRQ_CPU
+	select IRQ_TXX9
+	select I8259 if TOSHIBA_FPCIB0
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX49XX
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -555,12 +557,11 @@ config TOSHIBA_RBTX4927
 
 config TOSHIBA_RBTX4938
 	bool "Toshiba RBTX4938 board"
-	select HAVE_STD_PC_SERIAL_PORT
 	select DMA_NONCOHERENT
-	select GENERIC_ISA_DMA
 	select HAS_TXX9_SERIAL
 	select HW_HAS_PCI
-	select I8259
+	select IRQ_CPU
+	select IRQ_TXX9
 	select SWAP_IO_SPACE
 	select SYS_HAS_CPU_TX49XX
 	select SYS_SUPPORTS_32BIT_KERNEL
@@ -604,7 +605,6 @@ source "arch/mips/sibyte/Kconfig"
 source "arch/mips/tx4927/Kconfig"
 source "arch/mips/tx4938/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
-source "arch/mips/philips/pnx8550/common/Kconfig"
 
 endmenu
 
@@ -693,9 +693,9 @@ config EARLY_PRINTK
 config SYS_HAS_EARLY_PRINTK
 	bool
 
-config GENERIC_ISA_DMA
+config HOTPLUG_CPU
 	bool
-	select ZONE_DMA
+	default n
 
 config I8259
 	bool
@@ -712,9 +712,13 @@ config MIPS_DISABLE_OBSOLETE_IDE
 config NO_IOPORT
 	def_bool n
 
+config GENERIC_ISA_DMA
+	bool
+	select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
+
 config GENERIC_ISA_DMA_SUPPORT_BROKEN
 	bool
-	select ZONE_DMA
+	select GENERIC_ISA_DMA
 
 config GENERIC_GPIO
 	bool
@@ -768,6 +772,9 @@ config IRQ_MSP_SLP
 config IRQ_MSP_CIC
 	bool
 
+config IRQ_TXX9
+	bool
+
 config MIPS_BOARDS_GEN
 	bool
 
@@ -1427,8 +1434,7 @@ config SB1_PASS_2_1_WORKAROUNDS
 	default y
 
 config 64BIT_PHYS_ADDR
-	bool "Support for 64-bit physical address space"
-	depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
+	bool
 
 config CPU_HAS_LLSC
 	bool

arch/mips/au1000/Kconfig

@@ -136,6 +136,7 @@ config SOC_AU1200
 
 config SOC_AU1X00
 	bool
+	select 64BIT_PHYS_ADDR
 	select SYS_HAS_CPU_MIPS32_R1
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_APM_EMULATION

arch/mips/au1000/common/gpio.c

@@ -131,12 +131,12 @@ int au1xxx_gpio_direction_input(unsigned gpio)
 {
 	if (gpio >= AU1XXX_GPIO_BASE)
 #if defined(CONFIG_SOC_AU1000)
-		;
+		return -ENODEV;
 #else
 		return au1xxx_gpio2_direction_input(gpio);
 #endif
-	else
-		return au1xxx_gpio1_direction_input(gpio);
+
+	return au1xxx_gpio1_direction_input(gpio);
 }
 
 EXPORT_SYMBOL(au1xxx_gpio_direction_input);
@@ -145,12 +145,12 @@ int au1xxx_gpio_direction_output(unsigned gpio, int value)
 {
 	if (gpio >= AU1XXX_GPIO_BASE)
 #if defined(CONFIG_SOC_AU1000)
-		;
+		return -ENODEV;
 #else
 		return au1xxx_gpio2_direction_output(gpio, value);
 #endif
-	else
-		return au1xxx_gpio1_direction_output(gpio, value);
+
+	return au1xxx_gpio1_direction_output(gpio, value);
 }
 
 EXPORT_SYMBOL(au1xxx_gpio_direction_output);

arch/mips/configs/bigsur_defconfig

@@ -663,8 +663,8 @@ CONFIG_MOXA_SMARTIO_NEW=m
 # CONFIG_SX is not set
 # CONFIG_RIO is not set
 # CONFIG_STALDRV is not set
-CONFIG_SIBYTE_SB1250_DUART=y
-CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
+CONFIG_SERIAL_SB1250_DUART=y
+CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
 
 #
 # Serial drivers

arch/mips/configs/sb1250-swarm_defconfig

@@ -655,8 +655,8 @@ CONFIG_MOXA_SMARTIO_NEW=m
 # CONFIG_SX is not set
 # CONFIG_RIO is not set
 # CONFIG_STALDRV is not set
-CONFIG_SIBYTE_SB1250_DUART=y
-CONFIG_SIBYTE_SB1250_DUART_CONSOLE=y
+CONFIG_SERIAL_SB1250_DUART=y
+CONFIG_SERIAL_SB1250_DUART_CONSOLE=y
 
 #
 # Serial drivers

arch/mips/jmr3927/rbhma3100/irq.c

@@ -45,9 +45,6 @@
 #error JMR3927_IRQ_END > NR_IRQS
 #endif
 
-#define irc_dlevel	0
-#define irc_elevel	1
-
 static unsigned char irc_level[TX3927_NUM_IR] = {
 	5, 5, 5, 5, 5, 5,	/* INT[5:0] */
 	7, 7,			/* SIO */
@@ -80,34 +77,6 @@ static void unmask_irq_ioc(unsigned int irq)
 	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
 }
 
-static void mask_irq_irc(unsigned int irq)
-{
-	unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
-	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
-	if (irq_nr & 1)
-		*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
-	else
-		*ilrp = (*ilrp & 0xff00) | irc_dlevel;
-	/* update IRCSR */
-	tx3927_ircptr->imr = 0;
-	tx3927_ircptr->imr = irc_elevel;
-	/* flush write buffer */
-	(void)tx3927_ircptr->ssr;
-}
-
-static void unmask_irq_irc(unsigned int irq)
-{
-	unsigned int irq_nr = irq - JMR3927_IRQ_IRC;
-	volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
-	if (irq_nr & 1)
-		*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
-	else
-		*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
-	/* update IRCSR */
-	tx3927_ircptr->imr = 0;
-	tx3927_ircptr->imr = irc_elevel;
-}
-
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned long cp0_cause = read_c0_cause();
@@ -168,10 +137,6 @@ void __init arch_init_irq(void)
 	/* clear PCI Reset interrupts */
 	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 
-	/* enable interrupt control */
-	tx3927_ircptr->cer = TX3927_IRCER_ICE;
-	tx3927_ircptr->imr = irc_elevel;
-
 	jmr3927_irq_init();
 
 	/* setup IOC interrupt 1 (PCI, MODEM) */
@@ -193,20 +158,13 @@ static struct irq_chip jmr3927_irq_ioc = {
 	.unmask = unmask_irq_ioc,
 };
 
-static struct irq_chip jmr3927_irq_irc = {
-	.name = "jmr3927_irc",
-	.ack = mask_irq_irc,
-	.mask = mask_irq_irc,
-	.mask_ack = mask_irq_irc,
-	.unmask = unmask_irq_irc,
-};
-
 static void __init jmr3927_irq_init(void)
 {
 	u32 i;
 
-	for (i = JMR3927_IRQ_IRC; i < JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC; i++)
-		set_irq_chip_and_handler(i, &jmr3927_irq_irc, handle_level_irq);
+	txx9_irq_init(TX3927_IRC_REG);
+	for (i = 0; i < TXx9_MAX_IR; i++)
+		txx9_irq_set_pri(i, irc_level[i]);
 	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
 		set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
 }

arch/mips/jmr3927/rbhma3100/setup.c

@@ -290,19 +290,6 @@ static void __init tx3927_setup(void)
 	       tx3927_ccfgptr->crir,
 	       tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 
-	/* IRC */
-	/* disable interrupt control */
-	tx3927_ircptr->cer = 0;
-	/* mask all IRC interrupts */
-	tx3927_ircptr->imr = 0;
-	for (i = 0; i < TX3927_NUM_IR / 2; i++) {
-		tx3927_ircptr->ilr[i] = 0;
-	}
-	/* setup IRC interrupt mode (Low Active) */
-	for (i = 0; i < TX3927_NUM_IR / 8; i++) {
-		tx3927_ircptr->cr[i] = 0;
-	}
-
 	/* TMR */
 	/* disable all timers */
 	for (i = 0; i < TX3927_NR_TMR; i++) {

arch/mips/kernel/Makefile

@@ -50,6 +50,7 @@ obj-$(CONFIG_IRQ_CPU)		+= irq_cpu.o
 obj-$(CONFIG_IRQ_CPU_RM7K)	+= irq-rm7000.o
 obj-$(CONFIG_IRQ_CPU_RM9K)	+= irq-rm9000.o
 obj-$(CONFIG_MIPS_BOARDS_GEN)	+= irq-msc01.o
+obj-$(CONFIG_IRQ_TXX9)		+= irq_txx9.o
 
 obj-$(CONFIG_32BIT)		+= scall32-o32.o
 obj-$(CONFIG_64BIT)		+= scall64-64.o

arch/mips/kernel/asm-offsets.c

@@ -232,6 +232,10 @@ void output_mm_defines(void)
 	constant("#define _PMD_T_LOG2    ", PMD_T_LOG2);
 	constant("#define _PTE_T_LOG2    ", PTE_T_LOG2);
 	linefeed;
+	constant("#define _PGD_ORDER     ", PGD_ORDER);
+	constant("#define _PMD_ORDER     ", PMD_ORDER);
+	constant("#define _PTE_ORDER     ", PTE_ORDER);
+	linefeed;
 	constant("#define _PMD_SHIFT     ", PMD_SHIFT);
 	constant("#define _PGDIR_SHIFT   ", PGDIR_SHIFT);
 	linefeed;

arch/mips/kernel/cpu-bugs64.c

@@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod)
 		".endr\n\t"
 		".set	pop"
 		:
-		: "n" (align), "n" (mod));
+		: "rn" (align), "rn" (mod));
 }
 
 static inline void mult_sh_align_mod(long *v1, long *v2, long *w,

arch/mips/kernel/irixsig.c

@@ -725,7 +725,7 @@ asmlinkage int irix_getcontext(struct pt_regs *regs)
 	       current->comm, current->pid, ctx);
 #endif
 
-	if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)));
+	if (!access_ok(VERIFY_WRITE, ctx, sizeof(*ctx)))
 		return -EFAULT;
 
 	error = __put_user(current->thread.irix_oldctx, &ctx->link);

arch/mips/kernel/irq_txx9.c

+/*
+ * linux/arch/mips/kernel/irq_txx9.c
+ *
+ * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
+ *          linux/arch/mips/tx4927/common/tx4927_irq.c,
+ *          linux/arch/mips/tx4938/common/irq.c
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         ahennessy@mvista.com
+ *         source@mvista.com
+ * Copyright (C) 2000-2001 Toshiba Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <asm/txx9irq.h>
+
+struct txx9_irc_reg {
+	u32 cer;
+	u32 cr[2];
+	u32 unused0;
+	u32 ilr[8];
+	u32 unused1[4];
+	u32 imr;
+	u32 unused2[7];
+	u32 scr;
+	u32 unused3[7];
+	u32 ssr;
+	u32 unused4[7];
+	u32 csr;
+};
+
+/* IRCER : Int. Control Enable */
+#define TXx9_IRCER_ICE	0x00000001
+
+/* IRCR : Int. Control */
+#define TXx9_IRCR_LOW	0x00000000
+#define TXx9_IRCR_HIGH	0x00000001
+#define TXx9_IRCR_DOWN	0x00000002
+#define TXx9_IRCR_UP	0x00000003
+#define TXx9_IRCR_EDGE(cr)	((cr) & 0x00000002)
+
+/* IRSCR : Int. Status Control */
+#define TXx9_IRSCR_EIClrE	0x00000100
+#define TXx9_IRSCR_EIClr_MASK	0x0000000f
+
+/* IRCSR : Int. Current Status */
+#define TXx9_IRCSR_IF	0x00010000
+#define TXx9_IRCSR_ILV_MASK	0x00000700
+#define TXx9_IRCSR_IVL_MASK	0x0000001f
+
+#define irc_dlevel	0
+#define irc_elevel	1
+
+static struct txx9_irc_reg __iomem *txx9_ircptr __read_mostly;
+
+static struct {
+	unsigned char level;
+	unsigned char mode;
+} txx9irq[TXx9_MAX_IR] __read_mostly;
+
+static void txx9_irq_unmask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16 ) / 2];
+	int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
+
+	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
+		     | (txx9irq[irq_nr].level << ofs),
+		     ilrp);
+#ifdef CONFIG_CPU_TX39XX
+	/* update IRCSR */
+	__raw_writel(0, &txx9_ircptr->imr);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+#endif
+}
+
+static inline void txx9_irq_mask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *ilrp = &txx9_ircptr->ilr[(irq_nr % 16) / 2];
+	int ofs = irq_nr / 16 * 16 + (irq_nr & 1) * 8;
+
+	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
+		     | (irc_dlevel << ofs),
+		     ilrp);
+#ifdef CONFIG_CPU_TX39XX
+	/* update IRCSR */
+	__raw_writel(0, &txx9_ircptr->imr);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+	/* flush write buffer */
+	__raw_readl(&txx9_ircptr->ssr);
+#else
+	mmiowb();
+#endif
+}
+
+static void txx9_irq_mask_ack(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+
+	txx9_irq_mask(irq);
+	/* clear edge detection */
+	if (unlikely(TXx9_IRCR_EDGE(txx9irq[irq_nr].mode)))
+		__raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr);
+}
+
+static int txx9_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 cr;
+	u32 __iomem *crp;
+	int ofs;
+	int mode;
+
+	if (flow_type & IRQF_TRIGGER_PROBE)
+		return 0;
+	switch (flow_type & IRQF_TRIGGER_MASK) {
+	case IRQF_TRIGGER_RISING:	mode = TXx9_IRCR_UP;	break;
+	case IRQF_TRIGGER_FALLING:	mode = TXx9_IRCR_DOWN;	break;
+	case IRQF_TRIGGER_HIGH:	mode = TXx9_IRCR_HIGH;	break;
+	case IRQF_TRIGGER_LOW:	mode = TXx9_IRCR_LOW;	break;
+	default:
+		return -EINVAL;
+	}
+	crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8];
+	cr = __raw_readl(crp);
+	ofs = (irq_nr & (8 - 1)) * 2;
+	cr &= ~(0x3 << ofs);
+	cr |= (mode & 0x3) << ofs;
+	__raw_writel(cr, crp);
+	txx9irq[irq_nr].mode = mode;
+	return 0;
+}
+
+static struct irq_chip txx9_irq_chip = {
+	.name		= "TXX9",
+	.ack		= txx9_irq_mask_ack,
+	.mask		= txx9_irq_mask,
+	.mask_ack	= txx9_irq_mask_ack,
+	.unmask		= txx9_irq_unmask,
+	.set_type	= txx9_irq_set_type,
+};
+
+void __init txx9_irq_init(unsigned long baseaddr)
+{
+	int i;
+
+	txx9_ircptr = ioremap(baseaddr, sizeof(struct txx9_irc_reg));
+	for (i = 0; i < TXx9_MAX_IR; i++) {
+		txx9irq[i].level = 4; /* middle level */
+		txx9irq[i].mode = TXx9_IRCR_LOW;
+		set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
+					 &txx9_irq_chip, handle_level_irq);
+	}
+
+	/* mask all IRC interrupts */
+	__raw_writel(0, &txx9_ircptr->imr);
+	for (i = 0; i < 8; i++)
+		__raw_writel(0, &txx9_ircptr->ilr[i]);
+	/* setup IRC interrupt mode (Low Active) */
+	for (i = 0; i < 2; i++)
+		__raw_writel(0, &txx9_ircptr->cr[i]);
+	/* enable interrupt control */
+	__raw_writel(TXx9_IRCER_ICE, &txx9_ircptr->cer);
+	__raw_writel(irc_elevel, &txx9_ircptr->imr);
+}
+
+int __init txx9_irq_set_pri(int irc_irq, int new_pri)
+{
+	int old_pri;
+
+	if ((unsigned int)irc_irq >= TXx9_MAX_IR)
+		return 0;
+	old_pri = txx9irq[irc_irq].level;
+	txx9irq[irc_irq].level = new_pri;
+	return old_pri;
+}
+
+int txx9_irq(void)
+{
+	u32 csr = __raw_readl(&txx9_ircptr->csr);
+
+	if (likely(!(csr & TXx9_IRCSR_IF)))
+		return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
+	return -1;
+}

arch/mips/kernel/machine_kexec.c

@@ -78,11 +78,8 @@ machine_kexec(struct kimage *image)
 	 */
 	local_irq_disable();
 
-	flush_icache_range(reboot_code_buffer,
-			   reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
-
 	printk("Will call new kernel at %08lx\n", image->start);
 	printk("Bye ...\n");
-	flush_cache_all();
+	__flush_cache_all();
 	((noretfun_t) reboot_code_buffer)();
 }

arch/mips/kernel/mips-mt.c

@@ -4,6 +4,7 @@
  */
 
 #include <linux/device.h>
+#include <linux/kallsyms.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/module.h>
@@ -84,8 +85,9 @@ void mips_mt_regdump(unsigned long mvpctl)
 				       read_vpe_c0_vpeconf0());
 				printk("   VPE%d.Status : %08lx\n",
 				       i, read_vpe_c0_status());
-				printk("   VPE%d.EPC : %08lx\n",
+				printk("   VPE%d.EPC : %08lx ",
 				       i, read_vpe_c0_epc());
+				print_symbol("%s\n", read_vpe_c0_epc());
 				printk("   VPE%d.Cause : %08lx\n",
 				       i, read_vpe_c0_cause());
 				printk("   VPE%d.Config7 : %08lx\n",
@@ -110,7 +112,8 @@ void mips_mt_regdump(unsigned long mvpctl)
 		}
 		printk("   TCStatus : %08lx\n", tcstatval);
 		printk("   TCBind : %08lx\n", read_tc_c0_tcbind());
-		printk("   TCRestart : %08lx\n", read_tc_c0_tcrestart());
+		printk("   TCRestart : %08lx ", read_tc_c0_tcrestart());
+		print_symbol("%s\n", read_tc_c0_tcrestart());
 		printk("   TCHalt : %08lx\n", haltval);
 		printk("   TCContext : %08lx\n", read_tc_c0_tccontext());
 		if (!haltval)

arch/mips/kernel/smp-mt.c

@@ -287,7 +287,7 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
  * (unsigned long)idle->thread_info the gp
  * assumes a 1:1 mapping of TC => VPE
  */
-void prom_boot_secondary(int cpu, struct task_struct *idle)
+void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
 {
 	struct thread_info *gp = task_thread_info(idle);
 	dvpe();
@@ -321,7 +321,7 @@ void prom_boot_secondary(int cpu, struct task_struct *idle)
 	evpe(EVPE_ENABLE);
 }
 
-void prom_init_secondary(void)
+void __cpuinit prom_init_secondary(void)
 {
 	/* Enable per-cpu interrupts */
 
@@ -330,7 +330,7 @@ void prom_init_secondary(void)
 	                (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7));
 }
 
-void prom_smp_finish(void)
+void __cpuinit prom_smp_finish(void)
 {
 	write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
 

arch/mips/kernel/smtc.c

@@ -28,8 +28,6 @@
  * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set.
  */
 
-#define MIPS_CPU_IPI_IRQ	1
-
 #define LOCK_MT_PRA() \
 	local_irq_save(flags); \
 	mtflags = dmt()

arch/mips/lib/Makefile

@@ -28,4 +28,4 @@ obj-$(CONFIG_CPU_TX49XX)	+= dump_tlb.o
 obj-$(CONFIG_CPU_VR41XX)	+= dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
-obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
+obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o

arch/mips/philips/pnx8550/common/Kconfig

-# Place holder