[PATCH] slab: enable runtime cache line size on i386

From: Manfred Spraul <manfred@colorfullife.com>

the attached patch switches the SLAB_HWCACHE_ALIGN alignment from the
compile time L1 cache line size to the runtime detected value for i386. 
x86-64 already uses the runtime detection.

include/asm-i386/processor.h

@@ -649,6 +649,8 @@ extern inline void prefetchw(const void *x)
 
 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 
+#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
+
 #ifdef CONFIG_SCHED_SMT
 #define ARCH_HAS_SCHED_DOMAIN
 #define ARCH_HAS_SCHED_WAKE_IDLE