Commit 8a52fd9f authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter

drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoder

... instead of "pipe", which is wrong.
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 32ae46bf
...@@ -1766,22 +1766,20 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, ...@@ -1766,22 +1766,20 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
} }
static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv, static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe) enum transcoder cpu_transcoder)
{ {
int reg;
u32 val; u32 val;
/* FDI relies on the transcoder */ /* FDI relies on the transcoder */
assert_fdi_tx_disabled(dev_priv, pipe); assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
assert_fdi_rx_disabled(dev_priv, pipe); assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
reg = TRANSCONF(pipe); val = I915_READ(_TRANSACONF);
val = I915_READ(reg);
val &= ~TRANS_ENABLE; val &= ~TRANS_ENABLE;
I915_WRITE(reg, val); I915_WRITE(_TRANSACONF, val);
/* wait for PCH transcoder off, transcoder state */ /* wait for PCH transcoder off, transcoder state */
if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
DRM_ERROR("failed to disable transcoder %d\n", pipe); DRM_ERROR("Failed to disable PCH transcoder\n");
} }
/** /**
...@@ -3630,7 +3628,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) ...@@ -3630,7 +3628,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (is_pch_port) { if (is_pch_port) {
ironlake_fdi_disable(crtc); ironlake_fdi_disable(crtc);
lpt_disable_pch_transcoder(dev_priv, pipe); lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
intel_disable_pch_pll(intel_crtc); intel_disable_pch_pll(intel_crtc);
ironlake_fdi_pll_disable(intel_crtc); ironlake_fdi_pll_disable(intel_crtc);
} }
......
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