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Commit 8bd26e3a authored by Paul Gortmaker's avatar Paul Gortmaker
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arm: delete __cpuinit/__CPUINIT usage from all ARM users 

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications.  For example, the fix in
commit 5e427ec2 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out.  Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit  -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings.  In any case, they are temporary and harmless.

This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code.  It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.

[1] https://lkml.org/lkml/2013/5/20/589

Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
parent 078a55fc
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Showing with 64 additions and 140 deletions
arch/arm/common/mcpm_platsmp.c
View file @ 8bd26e3a
......@@ -19,7 +19,7 @@
#include <asm/smp.h>
#include <asm/smp_plat.h>
static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned int mpidr, pcpu, pcluster, ret;
extern void secondary_startup(void);
......@@ -40,7 +40,7 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i
return 0;
}
static void __cpuinit mcpm_secondary_init(unsigned int cpu)
static void mcpm_secondary_init(unsigned int cpu)
{
mcpm_cpu_powered_up();
}
......
arch/arm/include/asm/arch_timer.h
View file @ 8bd26e3a
......@@ -89,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void)
return cval;
}
static inline void __cpuinit arch_counter_set_user_access(void)
static inline void arch_counter_set_user_access(void)
{
u32 cntkctl;
......
arch/arm/kernel/head-common.S
View file @ 8bd26e3a
......@@ -149,7 +149,6 @@ ENDPROC(lookup_processor_type)
* r5 = proc_info pointer in physical address space
* r9 = cpuid (preserved)
*/
__CPUINIT
__lookup_processor_type:
adr r3, __lookup_processor_type_data
ldmia r3, {r4 - r6}
......
arch/arm/kernel/head-nommu.S
View file @ 8bd26e3a
......@@ -87,7 +87,6 @@ ENTRY(stext)
ENDPROC(stext)
#ifdef CONFIG_SMP
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.
......
arch/arm/kernel/head.S
View file @ 8bd26e3a
......@@ -343,7 +343,6 @@ __turn_mmu_on_loc:
.long __turn_mmu_on_end
#if defined(CONFIG_SMP)
__CPUINIT
ENTRY(secondary_startup)
/*
* Common entry point for secondary CPUs.
......
arch/arm/kernel/hw_breakpoint.c
View file @ 8bd26e3a
......@@ -1020,7 +1020,7 @@ static void reset_ctrl_regs(void *unused)
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
}
static int __cpuinit dbg_reset_notify(struct notifier_block *self,
static int dbg_reset_notify(struct notifier_block *self,
unsigned long action, void *cpu)
{
if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE)
......@@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata dbg_reset_nb = {
static struct notifier_block dbg_reset_nb = {
.notifier_call = dbg_reset_notify,
};
......
arch/arm/kernel/perf_event_cpu.c
View file @ 8bd26e3a
......@@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
* UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
* junk values out of them.
*/
static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
unsigned long action, void *hcpu)
static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
void *hcpu)
{
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;
......@@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
return NOTIFY_OK;
}
static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
static struct notifier_block cpu_pmu_hotplug_notifier = {
.notifier_call = cpu_pmu_notify,
};
......
arch/arm/kernel/psci_smp.c
View file @ 8bd26e3a
......@@ -46,8 +46,7 @@
extern void secondary_startup(void);
static int __cpuinit psci_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (psci_ops.cpu_on)
return psci_ops.cpu_on(cpu_logical_map(cpu),
......
arch/arm/kernel/smp.c
View file @ 8bd26e3a
......@@ -58,7 +58,7 @@ struct secondary_data secondary_data;
* control for which core is the next to come out of the secondary
* boot "holding pen"
*/
volatile int __cpuinitdata pen_release = -1;
volatile int pen_release = -1;
enum ipi_msg_type {
IPI_WAKEUP,
......@@ -86,7 +86,7 @@ static unsigned long get_arch_pgd(pgd_t *pgd)
return pgdir >> ARCH_PGD_SHIFT;
}
int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
int __cpu_up(unsigned int cpu, struct task_struct *idle)
{
int ret;
......@@ -138,7 +138,7 @@ void __init smp_init_cpus(void)
smp_ops.smp_init_cpus();
}
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
int boot_secondary(unsigned int cpu, struct task_struct *idle)
{
if (smp_ops.smp_boot_secondary)
return smp_ops.smp_boot_secondary(cpu, idle);
......@@ -170,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu)
/*
* __cpu_disable runs on the processor to be shutdown.
*/
int __cpuinit __cpu_disable(void)
int __cpu_disable(void)
{
unsigned int cpu = smp_processor_id();
int ret;
......@@ -216,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died);
* called on the thread which is asking for a CPU to be shutdown -
* waits until shutdown has completed, or it is timed out.
*/
void __cpuinit __cpu_die(unsigned int cpu)
void __cpu_die(unsigned int cpu)
{
if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
pr_err("CPU%u: cpu didn't die\n", cpu);
......@@ -306,7 +306,7 @@ void __ref cpu_die(void)
* Called by both boot and secondaries to move global data into
* per-processor storage.
*/
static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
static void smp_store_cpu_info(unsigned int cpuid)
{
struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
......@@ -322,7 +322,7 @@ static void percpu_timer_setup(void);
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
*/
asmlinkage void __cpuinit secondary_start_kernel(void)
asmlinkage void secondary_start_kernel(void)
{
struct mm_struct *mm = &init_mm;
unsigned int cpu;
......@@ -521,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode,
{
}
static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt)
static void broadcast_timer_setup(struct clock_event_device *evt)
{
evt->name = "dummy_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT |
......@@ -550,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops)
}
#endif
static void __cpuinit percpu_timer_setup(void)
static void percpu_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
......
arch/arm/kernel/smp_twd.c
View file @ 8bd26e3a
......@@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init);
#endif
static void __cpuinit twd_calibrate_rate(void)
static void twd_calibrate_rate(void)
{
unsigned long count;
u64 waitjiffies;
......@@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np)
/*
* Setup the local clock events for a CPU.
*/
static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
static int twd_timer_setup(struct clock_event_device *clk)
{
struct clock_event_device **this_cpu_clk;
int cpu = smp_processor_id();
......@@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk)
return 0;
}
static struct local_timer_ops twd_lt_ops __cpuinitdata = {
static struct local_timer_ops twd_lt_ops = {
.setup = twd_timer_setup,
.stop = twd_timer_stop,
};
......
arch/arm/lib/delay.c
View file @ 8bd26e3a
......@@ -86,7 +86,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
}
}
unsigned long __cpuinit calibrate_delay_is_known(void)
unsigned long calibrate_delay_is_known(void)
{
delay_calibrated = true;
return lpj_fine;
......
arch/arm/mach-exynos/headsmp.S
View file @ 8bd26e3a
......@@ -13,8 +13,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
......
arch/arm/mach-exynos/platsmp.c
View file @ 8bd26e3a
......@@ -75,7 +75,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit exynos_secondary_init(unsigned int cpu)
static void exynos_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -90,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
unsigned long phys_cpu = cpu_logical_map(cpu);
......
arch/arm/mach-highbank/platsmp.c
View file @ 8bd26e3a
......@@ -24,7 +24,7 @@
extern void secondary_startup(void);
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
......
arch/arm/mach-imx/platsmp.c
View file @ 8bd26e3a
......@@ -53,7 +53,7 @@ void imx_scu_standby_enable(void)
writel_relaxed(val, scu_base);
}
static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
imx_set_cpu_jump(cpu, v7_secondary_startup);
imx_enable_cpu(cpu, true);
......
arch/arm/mach-keystone/platsmp.c
View file @ 8bd26e3a
......@@ -21,7 +21,7 @@
#include "keystone.h"
static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu,
static int keystone_smp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
unsigned long start = virt_to_phys(&secondary_startup);
......
arch/arm/mach-msm/headsmp.S
View file @ 8bd26e3a
......@@ -11,8 +11,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* MSM specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
......
arch/arm/mach-msm/platsmp.c
View file @ 8bd26e3a
......@@ -38,7 +38,7 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
static void __cpuinit msm_secondary_init(unsigned int cpu)
static void msm_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -54,7 +54,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static __cpuinit void prepare_cold_cpu(unsigned int cpu)
static void prepare_cold_cpu(unsigned int cpu)
{
int ret;
ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
......@@ -73,7 +73,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
"address\n");
}
static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
static int cold_boot_done;
......
arch/arm/mach-msm/timer.c
View file @ 8bd26e3a
......@@ -139,7 +139,7 @@ static struct clocksource msm_clocksource = {
};
#ifdef CONFIG_LOCAL_TIMERS
static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
static int msm_local_timer_setup(struct clock_event_device *evt)
{
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
......@@ -164,7 +164,7 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
disable_percpu_irq(evt->irq);
}
static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
static struct local_timer_ops msm_local_timer_ops = {
.setup = msm_local_timer_setup,
.stop = msm_local_timer_stop,
};
......
arch/arm/mach-mvebu/coherency.c
View file @ 8bd26e3a
......@@ -28,7 +28,7 @@
#include <asm/cacheflush.h>
#include "armada-370-xp.h"
unsigned long __cpuinitdata coherency_phys_base;
unsigned long coherency_phys_base;
static void __iomem *coherency_base;
static void __iomem *coherency_cpu_base;
......
arch/arm/mach-mvebu/headsmp.S
View file @ 8bd26e3a
......@@ -21,8 +21,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* Armada XP specific entry point for secondary CPUs.
* We add the CPU to the coherency fabric and then jump to secondary
......
arch/arm/mach-mvebu/platsmp.c
View file @ 8bd26e3a
......@@ -71,13 +71,12 @@ void __init set_secondary_cpus_clock(void)
}
}
static void __cpuinit armada_xp_secondary_init(unsigned int cpu)
static void armada_xp_secondary_init(unsigned int cpu)
{
armada_xp_mpic_smp_cpu_init();
}
static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
struct task_struct *idle)
static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
pr_info("Booting CPU %d\n", cpu);
......
arch/arm/mach-omap2/omap-headsmp.S
View file @ 8bd26e3a
......@@ -20,8 +20,6 @@
#include "omap44xx.h"
__CPUINIT
/* Physical address needed since MMU not enabled yet on secondary core */
#define AUX_CORE_BOOT0_PA 0x48281800
......
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View file @ 8bd26e3a
......@@ -291,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* @cpu : CPU ID
* @power_state: CPU low power state.
*/
int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int cpu_state = 0;
......
arch/arm/mach-omap2/omap-smp.c
View file @ 8bd26e3a
......@@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void)
return scu_base;
}
static void __cpuinit omap4_secondary_init(unsigned int cpu)
static void omap4_secondary_init(unsigned int cpu)
{
/*
* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
......@@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
static struct clockdomain *cpu1_clkdm;
static bool booted;
......
arch/arm/mach-omap2/omap-wakeupgen.c
View file @ 8bd26e3a
......@@ -323,8 +323,8 @@ static void irq_save_secure_context(void)
#endif
#ifdef CONFIG_HOTPLUG_CPU
static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
static int irq_cpu_hotplug_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;
......
arch/arm/mach-prima2/headsmp.S
View file @ 8bd26e3a
......@@ -9,8 +9,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
/*
* SIRFSOC specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
......
arch/arm/mach-prima2/platsmp.c
View file @ 8bd26e3a
......@@ -44,7 +44,7 @@ void __init sirfsoc_map_scu(void)
scu_base = (void __iomem *)SIRFSOC_VA(base);
}
static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
static void sirfsoc_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -65,7 +65,7 @@ static struct of_device_id rsc_ids[] = {
{},
};
static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
struct device_node *np;
......
arch/arm/mach-shmobile/headsmp-scu.S
View file @ 8bd26e3a
......@@ -23,7 +23,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
/*
* Boot code for secondary CPUs.
*
......
arch/arm/mach-shmobile/headsmp.S
View file @ 8bd26e3a
......@@ -14,8 +14,6 @@
#include <linux/init.h>
#include <asm/memory.h>
__CPUINIT
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup
......
arch/arm/mach-shmobile/smp-emev2.c
View file @ 8bd26e3a
......@@ -30,7 +30,7 @@
#define EMEV2_SCU_BASE 0x1e000000
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
return 0;
......
arch/arm/mach-shmobile/smp-r8a7779.c
View file @ 8bd26e3a
......@@ -81,7 +81,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
return ret ? ret : 1;
}
static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
struct r8a7779_pm_ch *ch = NULL;
int ret = -EIO;
......
arch/arm/mach-shmobile/smp-sh73a0.c
View file @ 8bd26e3a
......@@ -48,7 +48,7 @@ void __init sh73a0_register_twd(void)
}
#endif
static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
......
arch/arm/mach-socfpga/headsmp.S
View file @ 8bd26e3a
......@@ -10,7 +10,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
.arch armv7-a
ENTRY(secondary_trampoline)
......
arch/arm/mach-socfpga/platsmp.c
View file @ 8bd26e3a
......@@ -29,7 +29,7 @@
#include "core.h"
static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
......
arch/arm/mach-spear/generic.h
View file @ 8bd26e3a
......@@ -37,7 +37,7 @@ void __init spear13xx_l2x0_init(void);
void spear_restart(enum reboot_mode, const char *);
void spear13xx_secondary_startup(void);
void __cpuinit spear13xx_cpu_die(unsigned int cpu);
void spear13xx_cpu_die(unsigned int cpu);
extern struct smp_operations spear13xx_smp_ops;
......
arch/arm/mach-spear/platsmp.c
View file @ 8bd26e3a
......@@ -24,7 +24,7 @@ static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
static void spear13xx_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -40,7 +40,7 @@ static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
......
arch/arm/mach-sti/platsmp.c
View file @ 8bd26e3a
......@@ -27,7 +27,7 @@
#include "smp.h"
static void __cpuinit write_pen_release(int val)
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
......@@ -37,7 +37,7 @@ static void __cpuinit write_pen_release(int val)
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit sti_secondary_init(unsigned int cpu)
void sti_secondary_init(unsigned int cpu)
{
trace_hardirqs_off();
......@@ -54,7 +54,7 @@ void __cpuinit sti_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
......
arch/arm/mach-tegra/platsmp.c
View file @ 8bd26e3a
......@@ -35,7 +35,7 @@
static cpumask_t tegra_cpu_init_mask;
static void __cpuinit tegra_secondary_init(unsigned int cpu)
static void tegra_secondary_init(unsigned int cpu)
{
cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
}
......@@ -167,7 +167,7 @@ static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
return ret;
}
static int __cpuinit tegra_boot_secondary(unsigned int cpu,
static int tegra_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
......
arch/arm/mach-tegra/pm.c
View file @ 8bd26e3a
......@@ -191,7 +191,7 @@ static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
[TEGRA_SUSPEND_LP0] = "LP0",
};
static int __cpuinit tegra_suspend_enter(suspend_state_t state)
static int tegra_suspend_enter(suspend_state_t state)
{
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
......
arch/arm/mach-ux500/platsmp.c
View file @ 8bd26e3a
......@@ -54,7 +54,7 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
static void __cpuinit ux500_secondary_init(unsigned int cpu)
static void ux500_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -69,7 +69,7 @@ static void __cpuinit ux500_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
......
arch/arm/mach-zynq/common.h
View file @ 8bd26e3a
......@@ -27,7 +27,7 @@ extern void secondary_startup(void);
extern char zynq_secondary_trampoline;
extern char zynq_secondary_trampoline_jump;
extern char zynq_secondary_trampoline_end;
extern int __cpuinit zynq_cpun_start(u32 address, int cpu);
extern int zynq_cpun_start(u32 address, int cpu);
extern struct smp_operations zynq_smp_ops __initdata;
#endif
......
arch/arm/mach-zynq/headsmp.S
View file @ 8bd26e3a
......@@ -9,8 +9,6 @@
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
ENTRY(zynq_secondary_trampoline)
ldr r0, [pc]
bx r0
......
arch/arm/mach-zynq/platsmp.c
View file @ 8bd26e3a
......@@ -30,11 +30,11 @@
/*
* Store number of cores in the system
* Because of scu_get_core_count() must be in __init section and can't
* be called from zynq_cpun_start() because it is in __cpuinit section.
* be called from zynq_cpun_start() because it is not in __init section.
*/
static int ncores;
int __cpuinit zynq_cpun_start(u32 address, int cpu)
int zynq_cpun_start(u32 address, int cpu)
{
u32 trampoline_code_size = &zynq_secondary_trampoline_end -
&zynq_secondary_trampoline;
......@@ -92,7 +92,7 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu)
}
EXPORT_SYMBOL(zynq_cpun_start);
static int __cpuinit zynq_boot_secondary(unsigned int cpu,
static int zynq_boot_secondary(unsigned int cpu,
struct task_struct *idle)
{
return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
......
arch/arm/mm/proc-arm1020.S
View file @ 8bd26e3a
......@@ -443,8 +443,6 @@ ENTRY(cpu_arm1020_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1020_setup, #function
__arm1020_setup:
mov r0, #0
......
arch/arm/mm/proc-arm1020e.S
View file @ 8bd26e3a
......@@ -425,8 +425,6 @@ ENTRY(cpu_arm1020e_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1020e_setup, #function
__arm1020e_setup:
mov r0, #0
......
arch/arm/mm/proc-arm1022.S
View file @ 8bd26e3a
......@@ -407,8 +407,6 @@ ENTRY(cpu_arm1022_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1022_setup, #function
__arm1022_setup:
mov r0, #0
......
arch/arm/mm/proc-arm1026.S
View file @ 8bd26e3a
......@@ -396,9 +396,6 @@ ENTRY(cpu_arm1026_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm1026_setup, #function
__arm1026_setup:
mov r0, #0
......
arch/arm/mm/proc-arm720.S
View file @ 8bd26e3a
......@@ -116,8 +116,6 @@ ENTRY(cpu_arm720_reset)
ENDPROC(cpu_arm720_reset)
.popsection
__CPUINIT
.type __arm710_setup, #function
__arm710_setup:
mov r0, #0
......
arch/arm/mm/proc-arm740.S
View file @ 8bd26e3a
......@@ -60,8 +60,6 @@ ENTRY(cpu_arm740_reset)
ENDPROC(cpu_arm740_reset)
.popsection
__CPUINIT
.type __arm740_setup, #function
__arm740_setup:
mov r0, #0
......
arch/arm/mm/proc-arm7tdmi.S
View file @ 8bd26e3a
......@@ -51,8 +51,6 @@ ENTRY(cpu_arm7tdmi_reset)
ENDPROC(cpu_arm7tdmi_reset)
.popsection
__CPUINIT
.type __arm7tdmi_setup, #function
__arm7tdmi_setup:
mov pc, lr
......
arch/arm/mm/proc-arm920.S
View file @ 8bd26e3a
......@@ -410,8 +410,6 @@ ENTRY(cpu_arm920_do_resume)
ENDPROC(cpu_arm920_do_resume)
#endif
__CPUINIT
.type __arm920_setup, #function
__arm920_setup:
mov r0, #0
......
arch/arm/mm/proc-arm922.S
View file @ 8bd26e3a
......@@ -388,8 +388,6 @@ ENTRY(cpu_arm922_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm922_setup, #function
__arm922_setup:
mov r0, #0
......
arch/arm/mm/proc-arm925.S
View file @ 8bd26e3a
......@@ -438,8 +438,6 @@ ENTRY(cpu_arm925_set_pte_ext)
#endif /* CONFIG_MMU */
mov pc, lr
__CPUINIT
.type __arm925_setup, #function
__arm925_setup:
mov r0, #0
......
arch/arm/mm/proc-arm926.S
View file @ 8bd26e3a
......@@ -425,8 +425,6 @@ ENTRY(cpu_arm926_do_resume)
ENDPROC(cpu_arm926_do_resume)
#endif
__CPUINIT
.type __arm926_setup, #function
__arm926_setup:
mov r0, #0
......
arch/arm/mm/proc-arm940.S
View file @ 8bd26e3a
......@@ -273,8 +273,6 @@ ENDPROC(arm940_dma_unmap_area)
@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
define_cache_functions arm940
__CPUINIT
.type __arm940_setup, #function
__arm940_setup:
mov r0, #0
......
arch/arm/mm/proc-arm946.S
View file @ 8bd26e3a
......@@ -326,8 +326,6 @@ ENTRY(cpu_arm946_dcache_clean_area)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
__CPUINIT
.type __arm946_setup, #function
__arm946_setup:
mov r0, #0
......
arch/arm/mm/proc-arm9tdmi.S
View file @ 8bd26e3a
......@@ -51,8 +51,6 @@ ENTRY(cpu_arm9tdmi_reset)
ENDPROC(cpu_arm9tdmi_reset)
.popsection
__CPUINIT
.type __arm9tdmi_setup, #function
__arm9tdmi_setup:
mov pc, lr
......
arch/arm/mm/proc-fa526.S
View file @ 8bd26e3a
......@@ -135,8 +135,6 @@ ENTRY(cpu_fa526_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __fa526_setup, #function
__fa526_setup:
/* On return of this routine, r0 must carry correct flags for CFG register */
......
arch/arm/mm/proc-feroceon.S
View file @ 8bd26e3a
......@@ -514,8 +514,6 @@ ENTRY(cpu_feroceon_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __feroceon_setup, #function
__feroceon_setup:
mov r0, #0
......
arch/arm/mm/proc-mohawk.S
View file @ 8bd26e3a
......@@ -383,8 +383,6 @@ ENTRY(cpu_mohawk_do_resume)
ENDPROC(cpu_mohawk_do_resume)
#endif
__CPUINIT
.type __mohawk_setup, #function
__mohawk_setup:
mov r0, #0
......
arch/arm/mm/proc-sa110.S
View file @ 8bd26e3a
......@@ -159,8 +159,6 @@ ENTRY(cpu_sa110_set_pte_ext)
#endif
mov pc, lr
__CPUINIT
.type __sa110_setup, #function
__sa110_setup:
mov r10, #0
......
arch/arm/mm/proc-sa1100.S
View file @ 8bd26e3a
......@@ -198,8 +198,6 @@ ENTRY(cpu_sa1100_do_resume)
ENDPROC(cpu_sa1100_do_resume)
#endif
__CPUINIT
.type __sa1100_setup, #function
__sa1100_setup:
mov r0, #0
......
arch/arm/mm/proc-v6.S
View file @ 8bd26e3a
......@@ -180,8 +180,6 @@ ENDPROC(cpu_v6_do_resume)
.align
__CPUINIT
/*
* __v6_setup
*
......
arch/arm/mm/proc-v7-2level.S
View file @ 8bd26e3a
......@@ -160,8 +160,6 @@ ENDPROC(cpu_v7_set_pte_ext)
mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
.endm
__CPUINIT
/* AT
* TFR EV X F I D LR S
* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
......@@ -172,5 +170,3 @@ ENDPROC(cpu_v7_set_pte_ext)
.type v7_crval, #object
v7_crval:
crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
.previous
arch/arm/mm/proc-v7-3level.S
View file @ 8bd26e3a
......@@ -140,8 +140,6 @@ ENDPROC(cpu_v7_set_pte_ext)
mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
.endm
__CPUINIT
/*
* AT
* TFR EV X F IHD LR S
......@@ -153,5 +151,3 @@ ENDPROC(cpu_v7_set_pte_ext)
.type v7_crval, #object
v7_crval:
crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
.previous
arch/arm/mm/proc-v7.S
View file @ 8bd26e3a
......@@ -167,8 +167,6 @@ ENDPROC(cpu_pj4b_do_idle)
#endif
__CPUINIT
/*
* __v7_setup
*
......
arch/arm/mm/proc-xsc3.S
View file @ 8bd26e3a
......@@ -446,8 +446,6 @@ ENTRY(cpu_xsc3_do_resume)
ENDPROC(cpu_xsc3_do_resume)
#endif
__CPUINIT
.type __xsc3_setup, #function
__xsc3_setup:
mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
......
arch/arm/mm/proc-xscale.S
View file @ 8bd26e3a
......@@ -558,8 +558,6 @@ ENTRY(cpu_xscale_do_resume)
ENDPROC(cpu_xscale_do_resume)
#endif
__CPUINIT
.type __xscale_setup, #function
__xscale_setup:
mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
......
arch/arm/plat-versatile/platsmp.c
View file @ 8bd26e3a
......@@ -23,7 +23,7 @@
* observers, irrespective of whether they're taking part in coherency
* or not. This is necessary for the hotplug code to work reliably.
*/
static void __cpuinit write_pen_release(int val)
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
......@@ -33,7 +33,7 @@ static void __cpuinit write_pen_release(int val)
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit versatile_secondary_init(unsigned int cpu)
void versatile_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
......@@ -48,7 +48,7 @@ void __cpuinit versatile_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
......
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