Commit 8c04f7a3 authored by Romain Perier's avatar Romain Perier Committed by Heiko Stuebner

clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs

Signed-off-by: default avatarRomain Perier <romain.perier@collabora.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 2bd6bf03
...@@ -156,6 +156,7 @@ ...@@ -156,6 +156,7 @@
#define PCLK_ISP 366 #define PCLK_ISP 366
#define PCLK_VIP 367 #define PCLK_VIP 367
#define PCLK_WDT 368 #define PCLK_WDT 368
#define PCLK_EFUSE256 369
/* hclk gates */ /* hclk gates */
#define HCLK_SFC 448 #define HCLK_SFC 448
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment