[PATCH] make irqaction use a cpu mask

From: William Lee Irwin III <wli@holomorphy.com>

The following patch makes irqaction's ->mask a cpumask as it was intended
to be and wraps up the rest of the sweep.  Only struct irqaction is
usefully greppable, so there may be some assignments to ->mask missing
still.  This removes more code than it adds.

From: William Lee Irwin III <wli@holomorphy.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/alpha/kernel/irq.c

@@ -416,7 +416,7 @@ request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/arm/kernel/irq.c

@@ -674,7 +674,7 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
 
 	action->handler = handler;
 	action->flags = irq_flags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/arm/mach-clps7500/core.c

@@ -188,7 +188,7 @@ static struct irqchip clps7500_no_chip = {
 	.unmask	= cl7500_no_action,
 };
 
-static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL };
+static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
 
 static void __init clps7500_init_irq(void)
 {

arch/arm26/kernel/irq.c

@@ -549,7 +549,7 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
 
 	action->handler = handler;
 	action->flags = irq_flags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/cris/arch-v10/kernel/time.c

@@ -253,7 +253,7 @@ timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  */
 
 static struct irqaction irq2  = { timer_interrupt, SA_SHIRQ | SA_INTERRUPT,
-				  0, "timer", NULL, NULL};
+				  CPU_MASK_NONE, "timer", NULL, NULL};
 
 void __init
 time_init(void)

arch/cris/kernel/irq.c

@@ -240,7 +240,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/i386/kernel/i8259.c

@@ -332,7 +332,7 @@ static irqreturn_t math_error_irq(int cpl, void *dev_id, struct pt_regs *regs)
  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  * so allow interrupt sharing.
  */
-static struct irqaction fpu_irq = { math_error_irq, 0, 0, "fpu", NULL, NULL };
+static struct irqaction fpu_irq = { math_error_irq, 0, CPU_MASK_NONE, "fpu", NULL, NULL };
 
 void __init init_ISA_irqs (void)
 {

arch/i386/kernel/irq.c

@@ -652,7 +652,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/i386/mach-default/setup.c

@@ -27,7 +27,7 @@ void __init pre_intr_init_hook(void)
 /*
  * IRQ2 is cascade interrupt to second interrupt controller
  */
-static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 /**
  * intr_init_hook - post gate setup interrupt initialisation
@@ -71,7 +71,7 @@ void __init trap_init_hook(void)
 {
 }
 
-static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
+static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
 
 /**
  * time_init_hook - do any specific initialisations for the system timer.

arch/i386/mach-voyager/setup.c

@@ -17,7 +17,7 @@ void __init pre_intr_init_hook(void)
 /*
  * IRQ2 is cascade interrupt to second interrupt controller
  */
-static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 void __init intr_init_hook(void)
 {
@@ -40,7 +40,7 @@ void __init trap_init_hook(void)
 {
 }
 
-static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
+static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
 
 void __init time_init_hook(void)
 {

arch/ia64/kernel/irq.c

@@ -607,7 +607,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/mips/baget/irq.c

@@ -325,7 +325,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;
@@ -389,7 +389,7 @@ static void write_err_interrupt(int irq, void *dev_id, struct pt_regs * regs)
 }
 
 static struct irqaction irq0  =
-{ write_err_interrupt, SA_INTERRUPT, 0, "bus write error", NULL, NULL};
+{ write_err_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "bus write error", NULL, NULL};
 
 void __init init_IRQ(void)
 {

arch/mips/baget/time.c

@@ -67,7 +67,7 @@ static void __init timer_enable(void)
 }
 
 static struct irqaction timer_irq  =
-{ timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
+{ timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
 
 void __init time_init(void)
 {

arch/mips/ddb5xxx/ddb5074/irq.c

@@ -24,7 +24,7 @@
 
 extern asmlinkage void ddbIRQ(void);
 
-static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
+static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
 
 #define M1543_PNP_CONFIG	0x03f0	/* PnP Config Port */
 #define M1543_PNP_INDEX		0x03f0	/* PnP Index Port */

arch/mips/ddb5xxx/ddb5476/irq.c

@@ -107,8 +107,8 @@ static void nile4_irq_setup(void)
 	/* memory resource acquire in ddb_setup */
 }
 
-static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
-static struct irqaction irq_error = { no_action, 0, 0, "error", NULL, NULL };
+static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
+static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
 
 extern asmlinkage void ddb5476_handle_int(void);
 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);

arch/mips/ddb5xxx/ddb5477/irq.c

@@ -77,7 +77,7 @@ extern void vrc5477_irq_init(u32 base);
 extern void mips_cpu_irq_init(u32 base);
 extern asmlinkage void ddb5477_handle_int(void);
 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);  
-static struct irqaction irq_cascade = { no_action, 0, 0, "cascade", NULL, NULL };
+static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
 
 void
 ddb5477_irq_setup(void)

arch/mips/gt64120/common/time.c

@@ -80,7 +80,7 @@ void gt64120_time_init(void)
 	timer.name = "timer";
 	timer.dev_id = NULL;
 	timer.next = NULL;
-	timer.mask = 0;
+	timer.mask = CPU_MASK_NONE;
 	irq_desc[GT_TIMER].action = &timer;
 
 	enable_irq(GT_TIMER);

arch/mips/jmr3927/rbhma3100/irq.c

@@ -301,7 +301,7 @@ static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 }
 
 static struct irqaction ioc_action = {
-	jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
+	jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
 };
 
 static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
@@ -318,7 +318,7 @@ static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 }
 
 static struct irqaction isac_action = {
-	jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
+	jmr3927_isac_interrupt, 0, CPU_MASK_NONE, "ISAC", NULL, NULL,
 };
 
 
@@ -327,7 +327,7 @@ static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * re
 	printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
 }
 static struct irqaction isaerr_action = {
-	jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
+	jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
 };
 
 static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
@@ -337,7 +337,7 @@ static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * re
 	       tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
 }
 static struct irqaction pcierr_action = {
-	jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
+	jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL,
 };
 
 int jmr3927_ether1_irq = 0;

arch/mips/kernel/irq.c

@@ -487,7 +487,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/mips/momentum/jaguar_atx/irq.c

@@ -42,7 +42,7 @@
 extern asmlinkage void jaguar_handle_int(void);
 
 static struct irqaction cascade_mv64340 = {
-	no_action, SA_INTERRUPT, 0, "MV64340-Cascade", NULL, NULL
+	no_action, SA_INTERRUPT, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
 };
 
 void __init init_IRQ(void)

arch/mips/momentum/ocelot_c/irq.c

@@ -53,11 +53,11 @@ extern void uart_irq_init(void);
 extern void cpci_irq_init(void);
 
 static struct irqaction cascade_fpga = {
-	no_action, SA_INTERRUPT, 0, "cascade via FPGA", NULL, NULL
+	no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
 };
 
 static struct irqaction cascade_mv64340 = {
-	no_action, SA_INTERRUPT, 0, "cascade via MV64340", NULL, NULL
+	no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
 };
 
 void __init init_IRQ(void)

arch/mips/sgi-ip32/ip32-irq.c

@@ -123,9 +123,9 @@ extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
 				      struct pt_regs *regs);
 
 struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT,
-				0, "CRIME memory error", NULL, NULL };
+			CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
 struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT,
-				0, "CRIME CPU error", NULL, NULL };
+			CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
 
 extern void ip32_handle_int(void);
 

arch/mips/sibyte/sb1250/irq.c

@@ -279,7 +279,7 @@ static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id,
 static struct irqaction sb1250_dummy_action = {
 	.handler = sb1250_dummy_handler,
 	.flags   = 0,
-	.mask    = 0,
+	.mask    = CPU_MASK_NONE,
 	.name    = "sb1250-private",
 	.next    = NULL,
 	.dev_id  = 0

arch/mips/tx4927/common/tx4927_irq.c

@@ -172,7 +172,7 @@ static struct hw_interrupt_type tx4927_irq_pic_type = {
 	.set_affinity	= NULL
 };
 
-#define TX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL }
+#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
 static struct irqaction tx4927_irq_pic_action =
 TX4927_PIC_ACTION(TX4927_PIC_NAME);
 

arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c

@@ -337,8 +337,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
 	return (sw_irq);
 }
 
-//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, 0, s, NULL, NULL }
-#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, 0, s, NULL, NULL }
+//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
+#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, CPU_MASK_NONE, s, NULL, NULL }
 static struct irqaction toshiba_rbtx4927_irq_ioc_action =
 TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
 #ifdef CONFIG_TOSHIBA_FPCIB0

arch/mips/vr4181/common/irq.c

@@ -180,9 +180,9 @@ extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 extern void mips_cpu_irq_init(u32 irq_base);
 
 static struct irqaction cascade =
-	{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
+	{ no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
 static struct irqaction reserved =
-	{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
+	{ no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
 
 void __init init_IRQ(void)
 {

arch/mips/vr41xx/common/giu.c

@@ -209,7 +209,7 @@ struct vr41xx_giuint_cascade {
 };
 
 static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
-static struct irqaction giu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction giu_cascade = {no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 static int no_irq_number(int irq)
 {

arch/mips/vr41xx/common/icu.c

@@ -288,7 +288,7 @@ static struct hw_interrupt_type giuint_irq_type = {
 
 /*=======================================================================*/
 
-static struct irqaction icu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction icu_cascade = {no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 static void __init vr41xx_icu_init(void)
 {

arch/parisc/kernel/irq.c

@@ -644,7 +644,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/ppc/kernel/irq.c

@@ -241,7 +241,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;			
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->dev_id = dev_id;
 	action->next = NULL;

arch/ppc64/kernel/irq.c

@@ -206,7 +206,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->dev_id = dev_id;
 	action->next = NULL;

arch/sh/cchips/hd6446x/hd64461/setup.c

@@ -134,7 +134,7 @@ int hd64461_irq_demux(int irq)
 	return __irq_demux(irq);
 }
 
-static struct irqaction irq0 = { hd64461_interrupt, SA_INTERRUPT, 0, "HD64461", NULL, NULL };
+static struct irqaction irq0 = { hd64461_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "HD64461", NULL, NULL };
 
 int __init setup_hd64461(void)
 {

arch/sh/cchips/hd6446x/hd64465/setup.c

@@ -154,7 +154,7 @@ int hd64465_irq_demux(int irq)
 	return irq;
 }
 
-static struct irqaction irq0  = { hd64465_interrupt, SA_INTERRUPT, 0, "HD64465", NULL, NULL};
+static struct irqaction irq0  = { hd64465_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "HD64465", NULL, NULL};
 
 
 static int __init setup_hd64465(void)

arch/sh/kernel/irq.c

@@ -436,7 +436,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/sh/kernel/time.c

@@ -391,7 +391,7 @@ static int __init sh_pclk_setup(char *str)
 }
 __setup("sh_pclk=", sh_pclk_setup);
 
-static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL};
+static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
 
 void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc)
 {

arch/sparc/kernel/irq.c

@@ -449,7 +449,7 @@ int request_fast_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->dev_id = NULL;
 	action->next = NULL;
@@ -529,7 +529,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/sparc/kernel/sun4d_irq.c

@@ -336,7 +336,7 @@ int sun4d_request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/sparc64/kernel/irq.c

@@ -118,10 +118,6 @@ static void register_irq_proc (unsigned int irq);
 		action->flags |= __irq_ino(irq) << 48;
 #define get_ino_in_irqaction(action)	(action->flags >> 48)
 
-#if NR_CPUS > 64
-#error irqaction embedded smp affinity does not work with > 64 cpus, FIXME
-#endif
-
 #define put_smpaff_in_irqaction(action, smpaff)	(action)->mask = (smpaff)
 #define get_smpaff_in_irqaction(action) 	((action)->mask)
 
@@ -458,7 +454,7 @@ int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_
 	action->next = NULL;
 	action->dev_id = dev_id;
 	put_ino_in_irqaction(action, irq);
-	put_smpaff_in_irqaction(action, 0);
+	put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 
 	if (tmp)
 		tmp->next = action;
@@ -694,7 +690,7 @@ static inline void redirect_intr(int cpu, struct ino_bucket *bp)
 	cpumask_t cpu_mask;
 	unsigned int buddy, ticks;
 
-	cpus_addr(cpu_mask)[0] = get_smpaff_in_irqaction(ap);
+	cpu_mask = get_smpaff_in_irqaction(ap);
 	cpus_and(cpu_mask, cpu_mask, cpu_online_map);
 	if (cpus_empty(cpu_mask))
 		cpu_mask = cpu_online_map;
@@ -715,7 +711,7 @@ static inline void redirect_intr(int cpu, struct ino_bucket *bp)
 		if (++buddy >= NR_CPUS)
 			buddy = 0;
 		if (++ticks > NR_CPUS) {
-			put_smpaff_in_irqaction(ap, 0);
+			put_smpaff_in_irqaction(ap, CPU_MASK_NONE);
 			goto out;
 		}
 	}
@@ -949,7 +945,7 @@ int request_fast_irq(unsigned int irq,
 	action->name = name;
 	action->next = NULL;
 	put_ino_in_irqaction(action, irq);
-	put_smpaff_in_irqaction(action, 0);
+	put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 
 	*(bucket->pil + irq_action) = action;
 	enable_irq(irq);
@@ -1167,45 +1163,6 @@ static struct proc_dir_entry * irq_dir [NUM_IVECS];
 
 #ifdef CONFIG_SMP
 
-#define HEX_DIGITS 16
-
-static unsigned int parse_hex_value (const char __user *buffer,
-		unsigned long count, unsigned long *ret)
-{
-	unsigned char hexnum [HEX_DIGITS];
-	unsigned long value;
-	int i;
-
-	if (!count)
-		return -EINVAL;
-	if (count > HEX_DIGITS)
-		count = HEX_DIGITS;
-	if (copy_from_user(hexnum, buffer, count))
-		return -EFAULT;
-
-	/*
-	 * Parse the first 8 characters as a hex string, any non-hex char
-	 * is end-of-string. '00e1', 'e1', '00E1', 'E1' are all the same.
-	 */
-	value = 0;
-
-	for (i = 0; i < count; i++) {
-		unsigned int c = hexnum[i];
-
-		switch (c) {
-			case '0' ... '9': c -= '0'; break;
-			case 'a' ... 'f': c -= 'a'-10; break;
-			case 'A' ... 'F': c -= 'A'-10; break;
-		default:
-			goto out;
-		}
-		value = (value << 4) | c;
-	}
-out:
-	*ret = value;
-	return 0;
-}
-
 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 			int count, int *eof, void *data)
 {
@@ -1214,7 +1171,7 @@ static int irq_affinity_read_proc (char *page, char **start, off_t off,
 	cpumask_t mask;
 	int len;
 
-	cpus_addr(mask)[0] = get_smpaff_in_irqaction(ap);
+	mask = get_smpaff_in_irqaction(ap);
 	if (cpus_empty(mask))
 		mask = cpu_online_map;
 
@@ -1225,7 +1182,7 @@ static int irq_affinity_read_proc (char *page, char **start, off_t off,
 	return len;
 }
 
-static inline void set_intr_affinity(int irq, unsigned long hw_aff)
+static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
 {
 	struct ino_bucket *bp = ivector_table + irq;
 
@@ -1243,22 +1200,17 @@ static int irq_affinity_write_proc (struct file *file, const char __user *buffer
 					unsigned long count, void *data)
 {
 	int irq = (long) data, full_count = count, err;
-	unsigned long new_value, i;
+	cpumask_t new_value;
 
-	err = parse_hex_value(buffer, count, &new_value);
+	err = cpumask_parse(buffer, count, new_value);
 
 	/*
 	 * Do not allow disabling IRQs completely - it's a too easy
 	 * way to make the system unusable accidentally :-) At least
 	 * one online CPU still has to be targeted.
 	 */
-	for (i = 0; i < NR_CPUS; i++) {
-		if ((new_value & (1UL << i)) != 0 &&
-		    !cpu_online(i))
-			new_value &= ~(1UL << i);
-	}
-
-	if (!new_value)
+	cpus_and(new_value, new_value, cpu_online_map);
+	if (cpus_empty(new_value))
 		return -EINVAL;
 
 	set_intr_affinity(irq, new_value);

arch/sparc64/kernel/smp.c

@@ -414,9 +414,6 @@ static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, c
  * packet, but we have no use for that.  However we do take advantage of
  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
  */
-#if NR_CPUS > 32
-#error Fixup cheetah_xcall_deliver Dave...
-#endif
 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 {
 	u64 pstate, ver;

arch/um/kernel/irq.c

@@ -419,7 +419,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/v850/kernel/fpga85e2c.c

@@ -168,5 +168,5 @@ static void make_reg_snap (int irq, void *dummy, struct pt_regs *regs)
 
 static int reg_snap_dev_id;
 static struct irqaction reg_snap_action = {
-	make_reg_snap, 0, 0, "reg_snap", &reg_snap_dev_id, 0
+	make_reg_snap, 0, CPU_MASK_NONE, "reg_snap", &reg_snap_dev_id, 0
 };

arch/v850/kernel/irq.c

@@ -392,7 +392,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/v850/kernel/time.c

@@ -203,7 +203,7 @@ static int timer_dev_id;
 static struct irqaction timer_irqaction = {
 	timer_interrupt,
 	SA_INTERRUPT,
-	0,
+	CPU_MASK_NONE,
 	"timer",
 	&timer_dev_id,
 	NULL

arch/x86_64/kernel/i8259.c

@@ -365,7 +365,7 @@ void __init init_8259A(int auto_eoi)
  * IRQ2 is cascade interrupt to second interrupt controller
  */
 
-static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL};
+static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
 
 void __init init_ISA_irqs (void)
 {

arch/x86_64/kernel/irq.c

@@ -488,7 +488,7 @@ int request_irq(unsigned int irq,
 
 	action->handler = handler;
 	action->flags = irqflags;
-	action->mask = 0;
+	cpus_clear(action->mask);
 	action->name = devname;
 	action->next = NULL;
 	action->dev_id = dev_id;

arch/x86_64/kernel/time.c

@@ -689,7 +689,7 @@ int __init time_setup(char *str)
 }
 
 static struct irqaction irq0 = {
-	timer_interrupt, SA_INTERRUPT, 0, "timer", NULL, NULL
+	timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL
 };
 
 extern void __init config_acpi_tables(void);

include/linux/interrupt.h

@@ -7,6 +7,7 @@
 #include <linux/linkage.h>
 #include <linux/bitops.h>
 #include <linux/preempt.h>
+#include <linux/cpumask.h>
 #include <asm/atomic.h>
 #include <asm/hardirq.h>
 #include <asm/ptrace.h>
@@ -35,7 +36,7 @@ typedef int irqreturn_t;
 struct irqaction {
 	irqreturn_t (*handler)(int, void *, struct pt_regs *);
 	unsigned long flags;
-	unsigned long mask;
+	cpumask_t mask;
 	const char *name;
 	void *dev_id;
 	struct irqaction *next;