Commit 8c99e7b0 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller

bnx2x: Pause settings

Pause settings
- 1G pause was not working due to missing write to the emac block
  (TX_MODE_FLOW_EN)
- The flow control should use the negotiated result (after autoneg) so
  we should save both the requested autoneg and the result
- The HW credits with flow control at 1G speed were not optimized and
  caused low throughput
- It is recommended to turn off flow control if the MTU is bigger than
  5000B due to internal buffers size
Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 57963ed9
This diff is collapsed.
...@@ -58,11 +58,13 @@ struct link_params { ...@@ -58,11 +58,13 @@ struct link_params {
u16 req_duplex; u16 req_duplex;
u16 req_flow_ctrl; u16 req_flow_ctrl;
u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
req_flow_ctrl is set to AUTO */
u16 req_line_speed; /* Also determine AutoNeg */ u16 req_line_speed; /* Also determine AutoNeg */
/* Device parameters */ /* Device parameters */
u8 mac_addr[6]; u8 mac_addr[6];
u16 mtu;
/* shmem parameters */ /* shmem parameters */
......
...@@ -1946,7 +1946,14 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp) ...@@ -1946,7 +1946,14 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
u8 rc; u8 rc;
/* Initialize link parameters structure variables */ /* Initialize link parameters structure variables */
bp->link_params.mtu = bp->dev->mtu; /* It is recommended to turn off RX FC for jumbo frames
for better performance */
if (IS_E1HMF(bp))
bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
else if (bp->dev->mtu > 5000)
bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
else
bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
bnx2x_acquire_phy_lock(bp); bnx2x_acquire_phy_lock(bp);
rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
......
...@@ -4966,6 +4966,7 @@ ...@@ -4966,6 +4966,7 @@
#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
#define EMAC_TX_MODE_FLOW_EN (1L<<4)
#define MISC_REGISTERS_GPIO_0 0 #define MISC_REGISTERS_GPIO_0 0
#define MISC_REGISTERS_GPIO_1 1 #define MISC_REGISTERS_GPIO_1 1
#define MISC_REGISTERS_GPIO_2 2 #define MISC_REGISTERS_GPIO_2 2
...@@ -5615,7 +5616,8 @@ Theotherbitsarereservedandshouldbezero*/ ...@@ -5615,7 +5616,8 @@ Theotherbitsarereservedandshouldbezero*/
#define MDIO_AN_REG_LINK_STATUS 0x8304 #define MDIO_AN_REG_LINK_STATUS 0x8304
#define MDIO_AN_REG_CL37_CL73 0x8370 #define MDIO_AN_REG_CL37_CL73 0x8370
#define MDIO_AN_REG_CL37_AN 0xffe0 #define MDIO_AN_REG_CL37_AN 0xffe0
#define MDIO_AN_REG_CL37_FD 0xffe4 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
#define MDIO_AN_REG_CL37_FC_LP 0xffe5
#define IGU_FUNC_BASE 0x0400 #define IGU_FUNC_BASE 0x0400
......
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