Commit 8d5b5d9c authored by Borislav Petkov's avatar Borislav Petkov

amd64_edac: Rename CPU PCI devices

Rename variables representing PCI devices to their BKDG names for faster
search and shorter, clearer code.
Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent b8cfa02f
This diff is collapsed.
...@@ -386,9 +386,7 @@ struct amd64_pvt { ...@@ -386,9 +386,7 @@ struct amd64_pvt {
struct low_ops *ops; struct low_ops *ops;
/* pci_device handles which we utilize */ /* pci_device handles which we utilize */
struct pci_dev *addr_f1_ctl; struct pci_dev *F1, *F2, *F3;
struct pci_dev *dram_f2_ctl;
struct pci_dev *misc_f3_ctl;
int mc_node_id; /* MC index of this MC node */ int mc_node_id; /* MC index of this MC node */
int ext_model; /* extended model value of this node */ int ext_model; /* extended model value of this node */
...@@ -518,8 +516,7 @@ struct low_ops { ...@@ -518,8 +516,7 @@ struct low_ops {
struct amd64_family_type { struct amd64_family_type {
const char *ctl_name; const char *ctl_name;
u16 addr_f1_ctl; u16 f1_id, f3_id;
u16 misc_f3_ctl;
struct low_ops ops; struct low_ops ops;
}; };
......
...@@ -122,15 +122,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci, ...@@ -122,15 +122,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
/* Form value to choose 16-byte section of cacheline */ /* Form value to choose 16-byte section of cacheline */
section = F10_NB_ARRAY_DRAM_ECC | section = F10_NB_ARRAY_DRAM_ECC |
SET_NB_ARRAY_ADDRESS(pvt->injection.section); SET_NB_ARRAY_ADDRESS(pvt->injection.section);
pci_write_config_dword(pvt->misc_f3_ctl, pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
F10_NB_ARRAY_ADDR, section);
word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word, word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
pvt->injection.bit_map); pvt->injection.bit_map);
/* Issue 'word' and 'bit' along with the READ request */ /* Issue 'word' and 'bit' along with the READ request */
pci_write_config_dword(pvt->misc_f3_ctl, pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
F10_NB_ARRAY_DATA, word_bits);
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
...@@ -157,15 +155,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci, ...@@ -157,15 +155,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
/* Form value to choose 16-byte section of cacheline */ /* Form value to choose 16-byte section of cacheline */
section = F10_NB_ARRAY_DRAM_ECC | section = F10_NB_ARRAY_DRAM_ECC |
SET_NB_ARRAY_ADDRESS(pvt->injection.section); SET_NB_ARRAY_ADDRESS(pvt->injection.section);
pci_write_config_dword(pvt->misc_f3_ctl, pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
F10_NB_ARRAY_ADDR, section);
word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word, word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
pvt->injection.bit_map); pvt->injection.bit_map);
/* Issue 'word' and 'bit' along with the READ request */ /* Issue 'word' and 'bit' along with the READ request */
pci_write_config_dword(pvt->misc_f3_ctl, pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
F10_NB_ARRAY_DATA, word_bits);
debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
......
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