drm/amd/display: add max_video_width cap to dc

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

@@ -2750,11 +2750,9 @@ bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
 
 bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
 {
-	struct dc *core_dc = dc;
-
 	/* TODO For now validates pixel format only */
-	if (core_dc->res_pool->funcs->validate_plane)
-		return core_dc->res_pool->funcs->validate_plane(plane_state) == DC_OK;
+	if (dc->res_pool->funcs->validate_plane)
+		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps) == DC_OK;
 
 	return true;
 }

drivers/gpu/drm/amd/display/dc/dc.h

@@ -57,6 +57,7 @@ struct dc_caps {
 	uint32_t max_downscale_ratio;
 	uint32_t i2c_speed_in_khz;
 	unsigned int max_cursor_size;
+	unsigned int max_video_width;
 	bool dcc_const_color;
 	bool dynamic_audio;
 };

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

@@ -743,7 +743,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool)
 	*pool = NULL;
 }
 
-enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state)
+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
 {
 
 	if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h

@@ -16,7 +16,7 @@ struct resource_pool *dce100_create_resource_pool(
 	uint8_t num_virtual_links,
 	struct dc *dc);
 
-enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state);
+enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps);
 
 enum dc_status dce100_add_stream_to_ctx(
 		struct dc *dc,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -1163,10 +1163,11 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool)
 	*pool = NULL;
 }
 
-enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state)
+static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
 {
 	if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
-			&& plane_state->src_rect.width > 3840)
+			&& caps->max_video_width != 0
+			&& plane_state->src_rect.width > caps->max_video_width)
 		return DC_FAIL_SURFACE_VALIDATE;
 
 	return DC_OK;
@@ -1222,6 +1223,7 @@ static bool construct(
 	/* max pipe num for ASIC before check pipe fuses */
 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
 
+	dc->caps.max_video_width = 3840;
 	dc->caps.max_downscale_ratio = 200;
 	dc->caps.i2c_speed_in_khz = 100;
 	dc->caps.max_cursor_size = 256;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -111,7 +111,7 @@ struct resource_funcs {
 			const struct resource_pool *pool,
 			struct dc_stream_state *stream);
 
-	enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state);
+	enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
 
 	enum dc_status (*add_stream_to_ctx)(
 			struct dc *dc,