Skip to content

L
linux
Commit 8eef6dea authored by Ryder Lee's avatar Ryder Lee Committed by Matthias Brugger
Browse files
Options

arm: dts: mediatek: modify audio related nodes for both MT2701 and MT7623 

Modify audio related nodes to reflect the actual usage in binding documents.
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 60cc43fc
Hide whitespace changes
Inline Side-by-side
Showing with 182 additions and 196 deletions
arch/arm/boot/dts/mt2701.dtsi
View file @ 8eef6dea
...@@ -426,104 +426,96 @@ spi2: spi@11017000 { ...@@ -426,104 +426,96 @@ spi2: spi@11017000 {
status = "disabled"; status = "disabled";
}; };
afe: audio-controller@11220000 { audsys: clock-controller@11220000 {
compatible = "mediatek,mt2701-audio"; compatible = "mediatek,mt2701-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>, reg = <0 0x11220000 0 0x2000>;
<0 0x112a0000 0 0x20000>; #clock-cells = <1>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; afe: audio-controller {
interrupt-names = "afe", "asys"; compatible = "mediatek,mt2701-audio";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_AUDIO>, interrupt-names = "afe", "asys";
<&topckgen CLK_TOP_AUD_MUX1_SEL>, power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
<&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_48K_TIMING>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_44K_TIMING>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_APLL_SEL>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD1PLL_98M>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD2PLL_90M>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_98M>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_294M>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D4>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D8>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUDPLL_D16>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUDPLL_D24>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&clk26m>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_SYSPLL1_D4>, <&audsys CLK_AUD_I2SO1>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, <&audsys CLK_AUD_I2SO2>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, <&audsys CLK_AUD_I2SO3>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&audsys CLK_AUD_I2SO4>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&audsys CLK_AUD_I2SIN1>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>, <&audsys CLK_AUD_I2SIN2>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>, <&audsys CLK_AUD_I2SIN3>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&audsys CLK_AUD_I2SIN4>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&audsys CLK_AUD_ASRCO1>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&audsys CLK_AUD_ASRCO2>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&audsys CLK_AUD_ASRCO3>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>, <&audsys CLK_AUD_ASRCO4>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>, <&audsys CLK_AUD_AFE>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&audsys CLK_AUD_AFE_CONN>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&audsys CLK_AUD_A1SYS>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&audsys CLK_AUD_A2SYS>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&audsys CLK_AUD_AFE_MRGIF>;
<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>, clock-names = "infra_sys_audio_clk",
<&topckgen CLK_TOP_ASM_M_SEL>, "top_audio_mux1_sel",
<&topckgen CLK_TOP_ASM_H_SEL>, "top_audio_mux2_sel",
<&topckgen CLK_TOP_UNIVPLL2_D4>, "top_audio_a1sys_hp",
<&topckgen CLK_TOP_UNIVPLL2_D2>, "top_audio_a2sys_hp",
<&topckgen CLK_TOP_SYSPLL_D5>; "i2s0_src_sel",
"i2s1_src_sel",
clock-names = "infra_sys_audio_clk", "i2s2_src_sel",
"top_audio_mux1_sel", "i2s3_src_sel",
"top_audio_mux2_sel", "i2s0_src_div",
"top_audio_mux1_div", "i2s1_src_div",
"top_audio_mux2_div", "i2s2_src_div",
"top_audio_48k_timing", "i2s3_src_div",
"top_audio_44k_timing", "i2s0_mclk_en",
"top_audpll_mux_sel", "i2s1_mclk_en",
"top_apll_sel", "i2s2_mclk_en",
"top_aud1_pll_98M", "i2s3_mclk_en",
"top_aud2_pll_90M", "i2so0_hop_ck",
"top_hadds2_pll_98M", "i2so1_hop_ck",
"top_hadds2_pll_294M", "i2so2_hop_ck",
"top_audpll", "i2so3_hop_ck",
"top_audpll_d4", "i2si0_hop_ck",
"top_audpll_d8", "i2si1_hop_ck",
"top_audpll_d16", "i2si2_hop_ck",
"top_audpll_d24", "i2si3_hop_ck",
"top_audintbus_sel", "asrc0_out_ck",
"clk_26m", "asrc1_out_ck",
"top_syspll1_d4", "asrc2_out_ck",
"top_aud_k1_src_sel", "asrc3_out_ck",
"top_aud_k2_src_sel", "audio_afe_pd",
"top_aud_k3_src_sel", "audio_afe_conn_pd",
"top_aud_k4_src_sel", "audio_a1sys_pd",
"top_aud_k5_src_sel", "audio_a2sys_pd",
"top_aud_k6_src_sel", "audio_mrgif_pd";
"top_aud_k1_src_div",
"top_aud_k2_src_div", assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
"top_aud_k3_src_div", <&topckgen CLK_TOP_AUD_MUX2_SEL>,
"top_aud_k4_src_div", <&topckgen CLK_TOP_AUD_MUX1_DIV>,
"top_aud_k5_src_div", <&topckgen CLK_TOP_AUD_MUX2_DIV>;
"top_aud_k6_src_div", assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
"top_aud_i2s1_mclk", <&topckgen CLK_TOP_AUD2PLL_90M>;
"top_aud_i2s2_mclk", assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
"top_aud_i2s3_mclk", };
"top_aud_i2s4_mclk",
"top_aud_i2s5_mclk",
"top_aud_i2s6_mclk",
"top_asm_m_sel",
"top_asm_h_sel",
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
}; };
mmsys: syscon@14000000 { mmsys: syscon@14000000 {
......
arch/arm/boot/dts/mt7623.dtsi
View file @ 8eef6dea
...@@ -545,105 +545,99 @@ spi2: spi@11017000 { ...@@ -545,105 +545,99 @@ spi2: spi@11017000 {
status = "disabled"; status = "disabled";
}; };
afe: audio-controller@11220000 { audsys: clock-controller@11220000 {
compatible = "mediatek,mt7623-audio", compatible = "mediatek,mt7623-audsys",
"mediatek,mt2701-audio"; "mediatek,mt2701-audsys",
reg = <0 0x11220000 0 0x2000>, "syscon";
<0 0x112a0000 0 0x20000>; reg = <0 0x11220000 0 0x2000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, #clock-cells = <1>;
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "afe", "asys";
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>, afe: audio-controller {
<&topckgen CLK_TOP_AUD_MUX1_SEL>, compatible = "mediatek,mt7623-audio",
<&topckgen CLK_TOP_AUD_MUX2_SEL>, "mediatek,mt2701-audio";
<&topckgen CLK_TOP_AUD_MUX1_DIV>, interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>, <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
<&topckgen CLK_TOP_AUD_48K_TIMING>, interrupt-names = "afe", "asys";
<&topckgen CLK_TOP_AUD_44K_TIMING>, power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
<&topckgen CLK_TOP_APLL_SEL>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD1PLL_98M>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD2PLL_90M>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_HADDS2PLL_98M>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_HADDS2PLL_294M>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUDPLL>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUDPLL_D4>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUDPLL_D8>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUDPLL_D16>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUDPLL_D24>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUDINTBUS_SEL>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&clk26m>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&topckgen CLK_TOP_SYSPLL1_D4>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&topckgen CLK_TOP_AUD_K5_SRC_SEL>, <&audsys CLK_AUD_I2SO1>,
<&topckgen CLK_TOP_AUD_K6_SRC_SEL>, <&audsys CLK_AUD_I2SO2>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&audsys CLK_AUD_I2SO3>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&audsys CLK_AUD_I2SO4>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&audsys CLK_AUD_I2SIN1>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&audsys CLK_AUD_I2SIN2>,
<&topckgen CLK_TOP_AUD_K5_SRC_DIV>, <&audsys CLK_AUD_I2SIN3>,
<&topckgen CLK_TOP_AUD_K6_SRC_DIV>, <&audsys CLK_AUD_I2SIN4>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&audsys CLK_AUD_ASRCO1>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&audsys CLK_AUD_ASRCO2>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&audsys CLK_AUD_ASRCO3>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&audsys CLK_AUD_ASRCO4>,
<&topckgen CLK_TOP_AUD_I2S5_MCLK>, <&audsys CLK_AUD_AFE>,
<&topckgen CLK_TOP_AUD_I2S6_MCLK>, <&audsys CLK_AUD_AFE_CONN>,
<&topckgen CLK_TOP_ASM_M_SEL>, <&audsys CLK_AUD_A1SYS>,
<&topckgen CLK_TOP_ASM_H_SEL>, <&audsys CLK_AUD_A2SYS>,
<&topckgen CLK_TOP_UNIVPLL2_D4>, <&audsys CLK_AUD_AFE_MRGIF>;
<&topckgen CLK_TOP_UNIVPLL2_D2>,
<&topckgen CLK_TOP_SYSPLL_D5>; clock-names = "infra_sys_audio_clk",
"top_audio_mux1_sel",
clock-names = "infra_sys_audio_clk", "top_audio_mux2_sel",
"top_audio_mux1_sel", "top_audio_a1sys_hp",
"top_audio_mux2_sel", "top_audio_a2sys_hp",
"top_audio_mux1_div", "i2s0_src_sel",
"top_audio_mux2_div", "i2s1_src_sel",
"top_audio_48k_timing", "i2s2_src_sel",
"top_audio_44k_timing", "i2s3_src_sel",
"top_audpll_mux_sel", "i2s0_src_div",
"top_apll_sel", "i2s1_src_div",
"top_aud1_pll_98M", "i2s2_src_div",
"top_aud2_pll_90M", "i2s3_src_div",
"top_hadds2_pll_98M", "i2s0_mclk_en",
"top_hadds2_pll_294M", "i2s1_mclk_en",
"top_audpll", "i2s2_mclk_en",
"top_audpll_d4", "i2s3_mclk_en",
"top_audpll_d8", "i2so0_hop_ck",
"top_audpll_d16", "i2so1_hop_ck",
"top_audpll_d24", "i2so2_hop_ck",
"top_audintbus_sel", "i2so3_hop_ck",
"clk_26m", "i2si0_hop_ck",
"top_syspll1_d4", "i2si1_hop_ck",
"top_aud_k1_src_sel", "i2si2_hop_ck",
"top_aud_k2_src_sel", "i2si3_hop_ck",
"top_aud_k3_src_sel", "asrc0_out_ck",
"top_aud_k4_src_sel", "asrc1_out_ck",
"top_aud_k5_src_sel", "asrc2_out_ck",
"top_aud_k6_src_sel", "asrc3_out_ck",
"top_aud_k1_src_div", "audio_afe_pd",
"top_aud_k2_src_div", "audio_afe_conn_pd",
"top_aud_k3_src_div", "audio_a1sys_pd",
"top_aud_k4_src_div", "audio_a2sys_pd",
"top_aud_k5_src_div", "audio_mrgif_pd";
"top_aud_k6_src_div",
"top_aud_i2s1_mclk", assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
"top_aud_i2s2_mclk", <&topckgen CLK_TOP_AUD_MUX2_SEL>,
"top_aud_i2s3_mclk", <&topckgen CLK_TOP_AUD_MUX1_DIV>,
"top_aud_i2s4_mclk", <&topckgen CLK_TOP_AUD_MUX2_DIV>;
"top_aud_i2s5_mclk", assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
"top_aud_i2s6_mclk", <&topckgen CLK_TOP_AUD2PLL_90M>;
"top_asm_m_sel", assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
"top_asm_h_sel", };
"top_univpll2_d4",
"top_univpll2_d2",
"top_syspll_d5";
}; };
mmc0: mmc@11230000 { mmc0: mmc@11230000 {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7