Commit 901781b9 authored by Daniel Vetter's avatar Daniel Vetter

drm/i915: use render gen to switch ring irq functions

Top-level interrupt bits are usually found in the display block. It
therefore makes sense to use HAS_PCH_SPLIT in i915_irq.c

But the irq stuff in intel_ring.c only concerns itself with render
core/gt-level interrupt sources. It therefore makes more sense to
switch based on gpu gen.

Kills a vlv special case.
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-Off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fad2596a
...@@ -687,7 +687,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring) ...@@ -687,7 +687,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
spin_lock(&ring->irq_lock); spin_lock(&ring->irq_lock);
if (ring->irq_refcount++ == 0) { if (ring->irq_refcount++ == 0) {
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) if (INTEL_INFO(dev)->gen >= 5)
ironlake_enable_irq(dev_priv, ironlake_enable_irq(dev_priv,
GT_PIPE_NOTIFY | GT_USER_INTERRUPT); GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
else else
...@@ -706,7 +706,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring) ...@@ -706,7 +706,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
spin_lock(&ring->irq_lock); spin_lock(&ring->irq_lock);
if (--ring->irq_refcount == 0) { if (--ring->irq_refcount == 0) {
if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) if (INTEL_INFO(dev)->gen >= 5)
ironlake_disable_irq(dev_priv, ironlake_disable_irq(dev_priv,
GT_USER_INTERRUPT | GT_USER_INTERRUPT |
GT_PIPE_NOTIFY); GT_PIPE_NOTIFY);
......
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