Commit 915166d9 authored by Russell King's avatar Russell King Committed by Russell King

Merge branch 'next-s3c' of git://aeryn.fluff.org.uk/bjdooks/linux into devel

parents 3eadd3b2 49fb88af
...@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, ...@@ -119,7 +119,7 @@ int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int shift = (off & 7) * 4; unsigned int shift = (off & 7) * 4;
u32 con; u32 con;
if (off < 8 && chip->chip.ngpio >= 8) if (off < 8 && chip->chip.ngpio > 8)
reg -= 4; reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) { if (s3c_gpio_is_cfg_special(cfg)) {
......
...@@ -191,7 +191,7 @@ static struct clk init_clocks[] = { ...@@ -191,7 +191,7 @@ static struct clk init_clocks[] = {
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_h,
.enable = s3c64xx_hclk_ctrl, .enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_UHOST, .ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .id = 0,
......
...@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { ...@@ -321,6 +321,11 @@ static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.get_pull = s3c_gpio_getpull_updown, .get_pull = s3c_gpio_getpull_updown,
}; };
int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
{
return IRQ_EINT(0) + pin;
}
static struct s3c_gpio_chip gpio_2bit[] = { static struct s3c_gpio_chip gpio_2bit[] = {
{ {
.base = S3C64XX_GPF_BASE, .base = S3C64XX_GPF_BASE,
...@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = { ...@@ -353,6 +358,7 @@ static struct s3c_gpio_chip gpio_2bit[] = {
.base = S3C64XX_GPN(0), .base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR, .ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN", .label = "GPN",
.to_irq = s3c64xx_gpio2int_gpn,
}, },
}, { }, {
.base = S3C64XX_GPO_BASE, .base = S3C64XX_GPO_BASE,
......
...@@ -88,11 +88,11 @@ ...@@ -88,11 +88,11 @@
#define S3C6400_CLKDIV2_SPI0_SHIFT (0) #define S3C6400_CLKDIV2_SPI0_SHIFT (0)
/* HCLK GATE Registers */ /* HCLK GATE Registers */
#define S3C_CLKCON_HCLK_BUS (1<<30) #define S3C_CLKCON_HCLK_3DSE (1<<31)
#define S3C_CLKCON_HCLK_SECUR (1<<29) #define S3C_CLKCON_HCLK_UHOST (1<<29)
#define S3C_CLKCON_HCLK_SDMA1 (1<<28) #define S3C_CLKCON_HCLK_SECUR (1<<28)
#define S3C_CLKCON_HCLK_SDMA2 (1<<27) #define S3C_CLKCON_HCLK_SDMA1 (1<<27)
#define S3C_CLKCON_HCLK_UHOST (1<<26) #define S3C_CLKCON_HCLK_SDMA0 (1<<26)
#define S3C_CLKCON_HCLK_IROM (1<<25) #define S3C_CLKCON_HCLK_IROM (1<<25)
#define S3C_CLKCON_HCLK_DDR1 (1<<24) #define S3C_CLKCON_HCLK_DDR1 (1<<24)
#define S3C_CLKCON_HCLK_DDR0 (1<<23) #define S3C_CLKCON_HCLK_DDR0 (1<<23)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment