Commit 91c665bd authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: create dcn21_link_encoder files

[Why]
DCN20 and DCN21 have different phy programming sequences.

[How]
Create a separate dcn21_link_encoder for Renoir
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c0fb59a4
...@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers { ...@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers {
type RDPCS_EXT_REFCLK_EN;\ type RDPCS_EXT_REFCLK_EN;\
type RDPCS_TX_FIFO_EN;\ type RDPCS_TX_FIFO_EN;\
type UNIPHY_LINK_ENABLE;\ type UNIPHY_LINK_ENABLE;\
type UNIPHY_CHANNEL0_XBAR_SOURCE;\
type UNIPHY_CHANNEL1_XBAR_SOURCE;\
type UNIPHY_CHANNEL2_XBAR_SOURCE;\
type UNIPHY_CHANNEL3_XBAR_SOURCE;\
type UNIPHY_CHANNEL0_INVERT;\ type UNIPHY_CHANNEL0_INVERT;\
type UNIPHY_CHANNEL1_INVERT;\ type UNIPHY_CHANNEL1_INVERT;\
type UNIPHY_CHANNEL2_INVERT;\ type UNIPHY_CHANNEL2_INVERT;\
...@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers { ...@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers {
type RDPCS_PHY_DPALT_DISABLE_ACK;\ type RDPCS_PHY_DPALT_DISABLE_ACK;\
type RDPCS_PHY_DP_MPLLB_V2I;\ type RDPCS_PHY_DP_MPLLB_V2I;\
type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\ type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
type RDPCS_PHY_RX_VREF_CTRL;\
type RDPCS_PHY_DP_MPLLB_CP_INT;\ type RDPCS_PHY_DP_MPLLB_CP_INT;\
type RDPCS_PHY_DP_MPLLB_CP_PROP;\ type RDPCS_PHY_DP_MPLLB_CP_PROP;\
type RDPCS_PHY_RX_REF_LD_VAL;\ type RDPCS_PHY_RX_REF_LD_VAL;\
type RDPCS_PHY_RX_VCO_LD_VAL;\ type RDPCS_PHY_RX_VCO_LD_VAL;\
type DPCSTX_DEBUG_CONFIG; \ type DPCSTX_DEBUG_CONFIG; \
type RDPCSTX_DEBUG_CONFIG type RDPCSTX_DEBUG_CONFIG; \
type RDPCS_PHY_DP_TX0_EQ_MAIN;\
type RDPCS_PHY_DP_TX0_EQ_PRE;\
type RDPCS_PHY_DP_TX0_EQ_POST;\
type RDPCS_PHY_DP_TX1_EQ_MAIN;\
type RDPCS_PHY_DP_TX1_EQ_PRE;\
type RDPCS_PHY_DP_TX1_EQ_POST;\
type RDPCS_PHY_DP_TX2_EQ_MAIN;\
type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
type RDPCS_PHY_DP_TX2_EQ_PRE;\
type RDPCS_PHY_DP_TX2_EQ_POST;\
type RDPCS_PHY_DP_TX3_EQ_MAIN;\
type RDPCS_PHY_DCO_RANGE;\
type RDPCS_PHY_DCO_FINETUNE;\
type RDPCS_PHY_DP_TX3_EQ_PRE;\
type RDPCS_PHY_DP_TX3_EQ_POST;\
type RDPCS_PHY_SUP_PRE_HP;\
type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
type UNIPHYA_SOFT_RESET;\
type UNIPHYB_SOFT_RESET;\
type UNIPHYC_SOFT_RESET;\
type UNIPHYD_SOFT_RESET;\
type UNIPHYE_SOFT_RESET;\
type UNIPHYF_SOFT_RESET
#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \ #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
type DIG_LANE0EN;\ type DIG_LANE0EN;\
......
...@@ -91,6 +91,13 @@ struct mpll_cfg { ...@@ -91,6 +91,13 @@ struct mpll_cfg {
uint32_t ref_range; uint32_t ref_range;
uint32_t ref_clk; uint32_t ref_clk;
bool hdmimode_enable; bool hdmimode_enable;
bool sup_pre_hp;
bool dp_tx0_vergdrv_byp;
bool dp_tx1_vergdrv_byp;
bool dp_tx2_vergdrv_byp;
bool dp_tx3_vergdrv_byp;
}; };
struct dpcssys_phy_seq_cfg { struct dpcssys_phy_seq_cfg {
......
# #
# Makefile for DCN21. # Makefile for DCN21.
DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o dcn21_link_encoder.o
CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4 CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
......
This diff is collapsed.
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_LINK_ENCODER__DCN21_H__
#define __DC_LINK_ENCODER__DCN21_H__
#include "dcn20/dcn20_link_encoder.h"
struct dcn21_link_encoder {
struct dcn10_link_encoder enc10;
struct dpcssys_phy_seq_cfg phy_seq_cfg;
};
void dcn21_link_encoder_enable_dp_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
enum clock_source_id clock_source);
void dcn21_link_encoder_construct(
struct dcn21_link_encoder *enc21,
const struct encoder_init_data *init_data,
const struct encoder_feature_support *enc_features,
const struct dcn10_link_enc_registers *link_regs,
const struct dcn10_link_enc_aux_registers *aux_regs,
const struct dcn10_link_enc_hpd_registers *hpd_regs,
const struct dcn10_link_enc_shift *link_shift,
const struct dcn10_link_enc_mask *link_mask);
#endif
...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
#include "dce110/dce110_hw_sequencer.h" #include "dce110/dce110_hw_sequencer.h"
#include "dcn20/dcn20_opp.h" #include "dcn20/dcn20_opp.h"
#include "dcn20/dcn20_dsc.h" #include "dcn20/dcn20_dsc.h"
#include "dcn20/dcn20_link_encoder.h" #include "dcn21/dcn21_link_encoder.h"
#include "dcn20/dcn20_stream_encoder.h" #include "dcn20/dcn20_stream_encoder.h"
#include "dce/dce_clock_source.h" #include "dce/dce_clock_source.h"
#include "dce/dce_audio.h" #include "dce/dce_audio.h"
...@@ -1463,6 +1463,87 @@ static const struct resource_create_funcs res_create_maximus_funcs = { ...@@ -1463,6 +1463,87 @@ static const struct resource_create_funcs res_create_maximus_funcs = {
.create_hwseq = dcn21_hwseq_create, .create_hwseq = dcn21_hwseq_create,
}; };
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 600000,
.hdmi_ycbcr420_supported = true,
.dp_ycbcr420_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true
};
#define link_regs(id, phyid)\
[id] = {\
LE_DCN10_REG_LIST(id), \
UNIPHY_DCN2_REG_LIST(phyid), \
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
}
static const struct dcn10_link_enc_registers link_enc_regs[] = {
link_regs(0, A),
link_regs(1, B),
link_regs(2, C),
link_regs(3, D),
link_regs(4, E),
};
#define aux_regs(id)\
[id] = {\
DCN2_AUX_REG_LIST(id)\
}
static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
aux_regs(0),
aux_regs(1),
aux_regs(2),
aux_regs(3),
aux_regs(4)
};
#define hpd_regs(id)\
[id] = {\
HPD_REG_LIST(id)\
}
static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
hpd_regs(0),
hpd_regs(1),
hpd_regs(2),
hpd_regs(3),
hpd_regs(4)
};
static const struct dcn10_link_enc_shift le_shift = {
LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT)
};
static const struct dcn10_link_enc_mask le_mask = {
LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK)
};
static struct link_encoder *dcn21_link_encoder_create(
const struct encoder_init_data *enc_init_data)
{
struct dcn21_link_encoder *enc21 =
kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
if (!enc21)
return NULL;
dcn21_link_encoder_construct(enc21,
enc_init_data,
&link_enc_feature,
&link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source],
&le_shift,
&le_mask);
return &enc21->enc10.base;
}
#define CTX ctx #define CTX ctx
#define REG(reg_name) \ #define REG(reg_name) \
...@@ -1478,7 +1559,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) ...@@ -1478,7 +1559,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
static struct resource_funcs dcn21_res_pool_funcs = { static struct resource_funcs dcn21_res_pool_funcs = {
.destroy = dcn21_destroy_resource_pool, .destroy = dcn21_destroy_resource_pool,
.link_enc_create = dcn20_link_encoder_create, .link_enc_create = dcn21_link_encoder_create,
.validate_bandwidth = dcn21_validate_bandwidth, .validate_bandwidth = dcn21_validate_bandwidth,
.add_stream_to_ctx = dcn20_add_stream_to_ctx, .add_stream_to_ctx = dcn20_add_stream_to_ctx,
.remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
......
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