Commit 92c06c66 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://ppc.bkbits.net/for-linus-ppc

into ppc970.osdl.org:/home/torvalds/v2.5/linux
parents 2c4dcfb7 bbb760e0
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS
default y
config FORCE
......
......@@ -16,13 +16,12 @@ HOSTCFLAGS += -Iarch/$(ARCH)/boot/include
BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd
bootdir-y := simple
bootdir-$(CONFIG_PPC_OF) := openfirmware
bootdir-$(CONFIG_PPC_PREP) += prep
bootdir-$(CONFIG_PPC_OF) += openfirmware
subdir-y := lib/ common/ images/
subdir-$(CONFIG_PPC_OF) += of1275/
# for cleaning
subdir- += simple/ openfirmware/ prep/
subdir- += simple/ openfirmware/
host-progs := $(addprefix utils/, addnote mknote hack-coff mkprep mkbugboot mktree)
......
......@@ -9,8 +9,5 @@
#
lib-y := string.o util.o misc-common.o \
serial_stub.o
lib-$(CONFIG_PPC_PREP) += mpc10x_memory.o
lib-$(CONFIG_LOPEC) += mpc10x_memory.o
lib-$(CONFIG_PAL4) += cpc700_memory.o
serial_stub.o bootinfo.o
lib-$(CONFIG_SERIAL_8250_CONSOLE) += ns16550.o
......@@ -14,7 +14,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -36,6 +36,13 @@ disable_6xx_mmu:
*/
li r8,MSR_IP|MSR_FP
mtmsr r8
isync
/* Test for a 601 */
mfpvr r10
srwi r10,r10,16
cmpi 0,r10,1 /* 601 ? */
beq .clearbats_601
/* Clear BATs */
li r8,0
......@@ -47,6 +54,7 @@ disable_6xx_mmu:
mtspr DBAT2L,r8
mtspr DBAT3U,r8
mtspr DBAT3L,r8
.clearbats_601:
mtspr IBAT0U,r8
mtspr IBAT0L,r8
mtspr IBAT1U,r8
......@@ -68,6 +76,7 @@ disable_6xx_mmu:
addi r8,r8,0x111 /* increment VSID */
addis r10,r10,0x1000 /* address of next segment */
bdnz 3b
blr
.globl disable_6xx_l1cache
disable_6xx_l1cache:
......
......@@ -2,4 +2,7 @@
# Makefile for some libs needed by zImage.
#
CFLAGS_kbd.o += -Idrivers/char
lib-y := zlib.o div64.o
lib-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o
......@@ -162,7 +162,7 @@ zImage.initrd: $(images)/vmlinux.initrd.coff \
$(images)/miboot.initrd.image
@echo ' kernel: $@ is ready ($<)'
TFTPIMAGE := /tftpboot/zImage.
TFTPIMAGE := /tftpboot/zImage
.PHONY: znetboot znetboot.initrd
znetboot: $(images)/vmlinux.coff \
......
# arch/ppc/boot/Makefile
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Tom Rini January 2001
#
# Originally:
# arch/ppc/boot/Makefile
# Copyright (C) 1994 by Linus Torvalds
# Adapted for PowerPC by Gary Thomas
# modified by Cort (cort@cs.nmt.edu)
#
TFTPIMAGE := /tftpboot/zImage.prep
ifeq ($(CONFIG_SMP),y)
TFTPIMAGE := $(TFTPIMAGE).smp
endif
boot-y := head.o misc.o
boot-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o
boot := arch/ppc/boot
common := $(boot)/common
utils := $(boot)/utils
bootlib := $(boot)/lib
images := $(boot)/images
simple := $(boot)/simple
of1275 := $(boot)/of1275
OBJCOPYFLAGS := -O elf32-powerpc
LIBS := $(common)/lib.a $(bootlib)/lib.a $(of1275)/lib.a
targets := $(boot-y) dummy.o ../simple/legacy.o
OBJS := $(addprefix $(obj)/,$(boot-y)) $(simple)/legacy.o
# Extra include search dirs
CFLAGS_kbd.o += -Idrivers/char
zImage: initrd :=
zImage: $(images)/zImage.prep
@echo ' kernel: $@ is ready ($<)'
zImage.initrd: initrd := .initrd
zImage.initrd: $(images)/zImage.initrd.prep
@echo ' kernel: $@ is ready ($<)'
$(images)/ramdisk.image.gz:
@echo ' MISSING $@'
@echo ' RAM disk image must be provided separately'
@/bin/false
OBJCOPYFLAGS_image.o := \
--add-section=.image=$(images)/vmlinux.gz \
--set-section-flags=.image=contents,alloc,load,readonly,data
targets += image.o
$(obj)/image.o: $(obj)/dummy.o $(images)/vmlinux.gz
$(call if_changed,objcopy)
OBJCOPYFLAGS_image.initrd.o := \
--add-section=.ramdisk=$(images)/ramdisk.image.gz \
--set-section-flags=.ramdisk=contents,alloc,load,readonly,data \
--add-section=.image=$(images)/vmlinux.gz \
--set-section-flags=.image=contents,alloc,load,readonly,data
targets += image.initrd.o
$(obj)/image.initrd.o: $(obj)/dummy.o $(images)/vmlinux.gz $(images)/ramdisk.image.gz
$(call if_changed,objcopy)
LDFLAGS_zImage.bin := -Ttext 0x00800000 -Bstatic -T
LDFLAGS_zImage.initrd.bin := -Ttext 0x00800000 -Bstatic -T
targets += zImage.bin
$(obj)/zImage.bin: $(boot)/ld.script $(OBJS) $(obj)/image.o $(LIBS)
$(call if_changed,ld)
targets += zImage.initrd.bin
$(obj)/zImage.initrd.bin: $(boot)/ld.script $(OBJS) $(obj)/image.initrd.o $(LIBS)
$(call if_changed,ld)
OBJCOPYFLAGS_zImage := -R .comment -R .stab -R .stabstr
OBJCOPYFLAGS_zImage.initrd := -R .comment -R .stab -R .stabstr
targets += zImage
$(obj)/zImage: %: %.bin FORCE
$(call if_changed,objcopy)
targets += zImage.initrd
$(obj)/zImage.initrd: %: %.bin FORCE
$(call if_changed,objcopy)
quiet_cmd_mkprep = MKPREP $@
cmd_mkprep = $(utils)/mkprep -pbp $< $@
$(images)/zImage.prep: $(obj)/zImage $(utils)/mkprep
$(call cmd,mkprep)
$(images)/zImage.initrd.prep: $(obj)/zImage.initrd $(utils)/mkprep
$(call cmd,mkprep)
#
# Convinient shorthands for various targets
#
floppy: zImage
dd if=$(images)/zImage.prep of=/dev/fd0H1440 bs=64b
znetboot : zImage
cp $(images)/zImage.prep $(TFTPIMAGE)
@echo ' kernel: $@ is ready ($<)'
znetboot.initrd : zImage.initrd
cp $(images)/zImage.initrd.prep $(TFTPIMAGE)
@echo ' kernel: $@ is ready ($<)'
int main(void)
{
return 0;
}
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include <asm/cache.h>
.text
/*
* Boot loader philosophy:
* ROM loads us to some arbitrary location
* Move the boot code to the link address (8M)
* Call decompress_kernel()
* Relocate the initrd, zimage and residual data to 8M
* Decompress the kernel to 0
* Jump to the kernel entry
* -- Cort
*/
.globl start
start:
bl start_
start_:
/* Enable, invalidate, Disable L1 icache/dcache */
li r8, 0
ori r8, r8, (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
mfspr r11,HID0
or r11,r11,r8
andc r10,r11,r8
isync
mtspr HID0,r8
sync
isync
mtspr HID0,r10
sync
isync
mr r11,r3 /* Save pointer to residual/board data */
/*
* Save the OF pointer to r25, but only if the entry point is in a sane
* location; if not we store 0. If there is no entry point, or it is
* invalid, we establish the default MSR value immediately. Otherwise,
* we defer doing that, to allow OF functions to be called, until we
* begin uncompressing the kernel.
*/
lis r3,0x0fff /* r3 = 0x0fffffff */
ori r3,r3,0xffff
subc r3,r3,r5 /* r3 = (r5 <= r3) ? ~0 : 0 */
subfe r3,r3,r3
nand r3,r3,r3
and. r5,r5,r3 /* r5 will be cleared if (r5 > r3) */
bne+ haveOF
li r3,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
mtmsr r3
isync
haveOF:
mr r25,r5
/* compute the size of the whole image in words. */
lis r4,start@h
ori r4,r4,start@l
lis r5,end@h
ori r5,r5,end@l
addi r5,r5,3 /* round up */
sub r5,r5,r4 /* end - start */
srwi r5,r5,2
mr r7,r5 /* Save for later use. */
/* check if we need to relocate ourselves to the link addr or were
* we loaded there to begin with -- Cort */
mflr r3
subi r3,r3,4 /* we get the nip, not the ip of the branch */
mr r8,r3
cmp 0,r3,r4
beq start_ldr /* If 0, we don't need to relocate */
/*
* no matter where we're loaded, move ourselves to -Ttext address
*/
relocate:
mflr r3 /* Compute code bias */
subi r3,r3,4
mr r8,r3
lis r4,start@h
ori r4,r4,start@l
mr r5,r7 /* Get the # of longwords again */
mtctr r5 /* Setup for loop */
li r6,0
subi r3,r3,4
subi r4,r4,4
00: lwzu r5,4(r3)
stwu r5,4(r4)
xor r6,r6,r5
bdnz 00b
lis r3,start_ldr@h
ori r3,r3,start_ldr@l
mtlr r3 /* Easiest way to do an absolute jump */
blr
start_ldr:
/* Some boards don't boot up with the I-cache enabled. Do that
* now because the decompress runs much faster that way.
* As a side effect, we have to ensure the data cache is not enabled
* so we can access the serial I/O without trouble.
*/
bl flush_instruction_cache
/* Clear all of BSS */
lis r3,edata@h
ori r3,r3,edata@l
lis r4,end@h
ori r4,r4,end@l
subi r3,r3,4
subi r4,r4,4
li r0,0
50: stwu r0,4(r3)
cmp 0,r3,r4
bne 50b
90: mr r9,r1 /* Save old stack pointer (in case it matters) */
lis r1,.stack@h
ori r1,r1,.stack@l
addi r1,r1,4096*2
subi r1,r1,256
li r2,0x000F /* Mask pointer to 16-byte boundary */
andc r1,r1,r2
/* Run loader */
mr r3,r8 /* Load point */
mr r4,r7 /* Program length */
mr r5,r6 /* Checksum */
mr r6,r11 /* Residual data */
mr r7,r25 /* Validated OFW interface */
bl decompress_kernel
/*
* We have to do this after decompress_kernel, just to make
* sure we don't wipe out things mapped in BATs which we need.
* -- Tom
*/
li r6,0
/* Test for a 601 */
mfspr r9,PVR
srwi r9,r9,16
cmpi 0,r9,1 /* 601 ? */
beq .clearbats_601
/* Clear BATS */
mtspr DBAT0U,r6
mtspr DBAT0L,r6
mtspr DBAT1U,r6
mtspr DBAT1L,r6
mtspr DBAT2U,r6
mtspr DBAT2L,r6
mtspr DBAT3U,r6
mtspr DBAT3L,r6
.clearbats_601:
mtspr IBAT0U,r6
mtspr IBAT0L,r6
mtspr IBAT1U,r6
mtspr IBAT1L,r6
mtspr IBAT2U,r6
mtspr IBAT2L,r6
mtspr IBAT3U,r6
mtspr IBAT3L,r6
isync
sync
sync
/* Set segment registers */
li r6,16 /* load up segment register values */
mtctr r6 /* for context 0 */
lis r6,0x2000 /* Ku = 1, VSID = 0 */
li r10,0
3: mtsrin r6,r10
addi r6,r6,0x111 /* increment VSID */
addis r10,r10,0x1000 /* address of next segment */
bdnz 3b
/* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
* and tell the kernel to start on the 4th instruction since we
* overwrite the first 3 sometimes (which are 'nop').
*/
li r9,0xc
mtlr r9
lis r10,0xdeadc0de@h
ori r10,r10,0xdeadc0de@l
li r9,0
stw r10,0(r9)
blr
.comm .stack,4096*2,4
......@@ -26,11 +26,12 @@ common := $(boot)/common
utils := $(boot)/utils
bootlib := $(boot)/lib
images := $(boot)/images
of1275 := $(boot)/of1275
tftpboot := /tftpboot
# Normally, we use the 'misc.c' file for decompress_kernel and
# whatnot. Sometimes we need to override this however.
misc-y := misc.o ../common/bootinfo.o
misc-y := misc.o
# Normally, we have our images end in .elf, but something we want to
# change this.
......@@ -89,6 +90,7 @@ zimageinitrd-$(motorola) := zImage.initrd-PPLUS
# Overrides previous assingment
extra.o-$(CONFIG_PPLUS) := legacy.o
extra.o-$(CONFIG_LOPEC) := mpc10x_memory.o
zimage-$(pcore) := zImage-STRIPELF
zimageinitrd-$(pcore) := zImage.initrd-STRIPELF
......@@ -96,6 +98,12 @@ zimageinitrd-$(pcore) := zImage.initrd-STRIPELF
end-$(pcore) := pcore
cacheflag-$(pcore) := -include $(clear_L2_L3)
zimage-$(CONFIG_PPC_PREP) := zImage-PPLUS
zimageinitrd-$(CONFIG_PPC_PREP) := zImage.initrd-PPLUS
extra.o-$(CONFIG_PPC_PREP) := legacy.o
misc-$(CONFIG_PPC_PREP) += misc-prep.o mpc10x_memory.o
end-$(CONFIG_PPC_PREP) := prep
end-$(CONFIG_SANDPOINT) := sandpoint
cacheflag-$(CONFIG_SANDPOINT) := -include $(clear_L2_L3)
......@@ -138,6 +146,9 @@ boot-$(CONFIG_GT64260_CONSOLE) += gt64260_tty.o
endif
LIBS := $(common)/lib.a $(bootlib)/lib.a
ifeq ($(CONFIG_PPC_PREP),y)
LIBS += $(of1275)/lib.a
endif
OBJS := $(addprefix $(obj)/,$(boot-y))
......@@ -199,10 +210,10 @@ $(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE)
$(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \
$(ENTRYPOINT)
$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.pplus
$(images)/zImage-PPLUS: $(obj)/zvmlinux $(utils)/mkprep $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y)
$(MKBUGBOOT) $(obj)/zvmlinux $(images)/zImage.bugboot
$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(MKPREP) $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.pplus
$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(utils)/mkprep $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y)
$(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot
......@@ -7,7 +7,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -57,10 +57,11 @@ start_:
isync
#endif
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6)
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
mr r29,r3 /* On the MBX860, r3 is the board info pointer.
* On the RPXSUPER, r3 points to the
* NVRAM configuration keys.
* On the RPXSUPER, r3 points to the NVRAM
* configuration keys.
* On PReP, r3 is the pointer to the residual data.
*/
#endif
......@@ -69,7 +70,36 @@ start_:
/* The following functions we call must not modify r3 or r4.....
*/
#ifdef CONFIG_6xx
/* On PReP we must look at the OpenFirmware pointer and sanity
* test it. On other platforms, we disable the MMU right now
* and other bits.
*/
#ifdef CONFIG_PPC_PREP
/*
* Save the OF pointer to r25, but only if the entry point is in a sane
* location; if not we store 0. If there is no entry point, or it is
* invalid, we establish the default MSR value immediately. Otherwise,
* we defer doing that, to allow OF functions to be called, until we
* begin uncompressing the kernel.
*/
lis r8,0x0fff /* r8 = 0x0fffffff */
ori r8,r8,0xffff
subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */
subfe r8,r8,r8
nand r8,r8,r8
and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */
bne+ haveOF
li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
mtmsr r8
isync
haveOF:
mr r25,r5
#else
bl disable_6xx_mmu
#endif
bl disable_6xx_l1cache
CLEAR_CACHES
......@@ -99,7 +129,7 @@ start_:
mr r3, r29
#endif
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6)
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
mr r4,r29 /* put the board info pointer where the relocate
* routine will find it
*/
......
......@@ -174,7 +174,8 @@ get_mem_size(void)
}
unsigned long
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
void *ign1, void *ign2)
{
int csr0;
int csr_id;
......
......@@ -99,7 +99,9 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
unsigned long initrd_loc, TotalMemory = 0;
serial_fixups();
#ifdef CONFIG_SERIAL_8250_CONSOLE
com_port = serial_init(0, NULL);
#endif
#ifdef CONFIG_44x
/* Reset MAL */
......@@ -269,7 +271,8 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
/* Allow decompress_kernel to be hooked into. This is the default. */
void * __attribute__ ((weak))
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
void *ign1, void *ign2)
{
return decompress_kernel(load_addr, num_words, cksum);
}
......@@ -52,8 +52,12 @@ MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
* the system. This assumes that the firmware has correctly set up the memory
* controller registers. On CONFIG_PPC_PREP, we know we are being called
* under a PReP memory map. On all other machines, we assume we are under
* a CHRP memory map.
* a CHRP memory map. Further, on CONFIG_PPC_MULTIPLATFORM we must rename
* this function.
*/
#ifdef CONFIG_PPC_MULTIPLATFORM
#define get_mem_size mpc10x_get_mem_size
#endif
unsigned long
get_mem_size(void)
{
......
......@@ -9,7 +9,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -101,8 +101,8 @@ relocate:
GETSYM(r4, __relocate_start)
GETSYM(r5, do_relocate)
sub r4,r5,r4 /* Get entry point for do_relocate in
add r6,r6,r4 * relocated section */
sub r4,r5,r4 /* Get entry point for do_relocate in */
add r6,r6,r4 /* relocated section */
/* This will return to the relocated do_relocate */
mtlr r6
......@@ -182,6 +182,7 @@ start_ldr:
mr r4,r7 /* Program length */
mr r5,r6 /* Checksum */
mr r6,r11 /* Residual data */
mr r7,r25 /* Validated OFW interface */
bl load_kernel
/*
......@@ -195,8 +196,18 @@ start_ldr:
/*
* Start at the begining.
*/
li r9,0x0000
li r9,0xc
mtlr r9
#ifdef CONFIG_PPC_MULTIPLATFORM
/* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
* and tell the kernel to start on the 4th instruction since we
* overwrite the first 3 sometimes (which are 'nop').
*/
lis r10,0xdeadc0de@h
ori r10,r10,0xdeadc0de@l
li r9,0
stw r10,0(r9)
#endif
blr
.comm .stack,4096*2,4
This diff is collapsed.
......@@ -79,6 +79,7 @@ spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
void die(const char * str, struct pt_regs * fp, long err)
{
static int die_counter;
int nl = 0;
console_verbose();
spin_lock_irq(&die_lock);
#ifdef CONFIG_PMAC_BACKLIGHT
......@@ -86,6 +87,16 @@ void die(const char * str, struct pt_regs * fp, long err)
set_backlight_level(BACKLIGHT_MAX);
#endif
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
#ifdef CONFIG_PREEMPT
printk("PREEMPT ");
nl = 1;
#endif
#ifdef CONFIG_SMP
printk("SMP NR_CPUS=%d ", NR_CPUS);
nl = 1;
#endif
if (nl)
printk("\n");
show_regs(fp);
spin_unlock_irq(&die_lock);
/* do_exit() should take care of panic'ing from an interrupt
......
......@@ -35,7 +35,7 @@
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/highmem.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
......@@ -143,15 +143,15 @@ void consistent_sync(void *vaddr, size_t size, int direction)
unsigned long end = start + size;
switch (direction) {
case PCI_DMA_NONE:
case DMA_NONE:
BUG();
case PCI_DMA_FROMDEVICE: /* invalidate only */
case DMA_FROMDEVICE: /* invalidate only */
invalidate_dcache_range(start, end);
break;
case PCI_DMA_TODEVICE: /* writeback only */
case DMA_TODEVICE: /* writeback only */
clean_dcache_range(start, end);
break;
case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
flush_dcache_range(start, end);
break;
}
......
......@@ -41,11 +41,11 @@ obj-$(CONFIG_MVME5100) += mvme5100_setup.o mvme5100_pci.o
obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore_setup.o pcore_pci.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus_pci.o pplus_setup.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce_setup.o spruce_pci.o
obj-$(CONFIG_SPRUCE) += spruce.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
......
/*
* arch/ppc/platforms/pplus.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greerinclude/asm-ppc/hawk.h
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PPC_PPLUS_H
#define __PPC_PPLUS_H
#include <asm/io.h>
/*
* Due to limiations imposed by legacy hardware (primaryily IDE controllers),
* the PPLUS boards operate using a PReP address map.
*
* From Processor (physical) -> PCI:
* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI -> Processor (physical):
* System Memory: 0x80000000 -> 0x00000000
*/
#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
/* PCI Memory space mapping info */
#define PPLUS_PCI_MEM_SIZE 0x30000000U
#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
#define PPLUS_PCI_MEM_START 0x00000000U
#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
/* PCI I/O space mapping info */
#define PPLUS_PCI_IO_SIZE 0x10000000U
#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
#define PPLUS_PCI_IO_START 0x00000000U
#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
/* System memory mapping info */
#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
/* Define base addresses for important sets of registers */
#define PPLUS_HAWK_SMC_BASE 0xfef80000U
#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
#define PPLUS_SYS_CONFIG_REG 0xfef80400U
#define PPLUS_L2_CONTROL_REG 0x8000081cU
#define PPLUS_VGA_MEM_BASE 0xf0000000U
extern int pplus_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long pplus_get_mem_size(unsigned int smc_base);
extern int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __PPC_PPLUS_H */
This diff is collapsed.
......@@ -49,6 +49,7 @@
#include <asm/cache.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mc146818rtc.h>
#include <asm/mk48t59.h>
#include <asm/prep_nvram.h>
#include <asm/raven.h>
......@@ -1023,8 +1024,10 @@ prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.time_init = todc_time_init;
if (_prep_type == _PREP_IBM) {
TODC_INIT(TODC_TYPE_MC146818, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.rtc_read_val = todc_mc146818_read_val;
ppc_md.rtc_write_val = todc_mc146818_write_val;
TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1),
8);
} else {
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
......
/*
* arch/ppc/platforms/spruce_setup.c
* arch/ppc/platforms/spruce.c
*
* Board setup routines for IBM Spruce
* Board and PCI setup routines for IBM Spruce
*
* Authors: Johnnie Peters <jpeters@mvista.com>
* Matt Porter <mporter@mvista.com>
* Author: MontaVista Software <source@mvista.com>
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* 2000-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -39,18 +38,73 @@
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <platforms/spruce.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/kgdb.h>
#include <syslib/cpc700.h>
extern void spruce_init_IRQ(void);
extern int spruce_get_irq(struct pt_regs *);
extern void spruce_setup_hose(void);
#include "spruce.h"
extern char cmd_line[];
static inline int
spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */
{24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */
{25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */
{26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
/*
* CPC700 PIC interrupt programming table
......@@ -122,7 +176,7 @@ spruce_early_serial_map(void)
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = uart_clk;
serial_req.irq = UART0_INT;
serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
serial_req.flags = ASYNC_BOOT_AUTOCONF;
serial_req.iotype = SERIAL_IO_MEM;
serial_req.membase = (u_char *)UART0_IO_BASE;
serial_req.regshift = 0;
......
......@@ -57,10 +57,10 @@
#define UART0_INT 3
#define UART1_INT 4
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
ASYNC_BOOT_AUTOCONF, \
iomem_base: UART##num##_IO_BASE, \
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
ASYNC_BOOT_AUTOCONF, \
iomem_base: (unsigned char *) UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#define SERIAL_PORT_DFNS \
......
/*
* arch/ppc/platforms/spruce_pci.c
*
* PCI support for IBM Spruce
*
* Author: Johnnie Peters
* jpeters@mvista.com
*
* 2000 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <platforms/spruce.h>
#include <syslib/cpc700.h>
static inline int
spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */
{24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */
{25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */
{26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
/*
* include/asm-ppc/spruce_serial.h
*
* Definitions for IBM Spruce reference board support
*
* Authors: Matt Porter and Johnnie Peters
* mporter@mvista.com
* jpeters@mvista.com
*
* 2000 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_SPRUCE_SERIAL_H
#define __ASMPPC_SPRUCE_SERIAL_H
#include <linux/config.h>
/* This is where the serial ports exist */
#define SPRUCE_SERIAL_1_ADDR 0xff600300
#define SPRUCE_SERIAL_2_ADDR 0xff600400
#define RS_TABLE_SIZE 4
/* Rate for the baud clock for the onboard serial chip */
#ifndef CONFIG_SPRUCE_BAUD_33M
#define BASE_BAUD (30000000 / 4 / 16)
#else
#define BASE_BAUD (33000000 / 4 / 16)
#endif
#ifndef SERIAL_MAGIC_KEY
#define kernel_debugger ppc_kernel_debug
#endif
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
#else
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
#endif
#define STD_SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, SPRUCE_SERIAL_1_ADDR, 3, STD_COM_FLAGS, /* ttyS0 */ \
iomem_base: (u8 *)SPRUCE_SERIAL_1_ADDR, \
io_type: SERIAL_IO_MEM }, \
{ 0, BASE_BAUD, SPRUCE_SERIAL_2_ADDR, 4, STD_COM_FLAGS, /* ttyS1 */ \
iomem_base: (u8 *)SPRUCE_SERIAL_2_ADDR, \
io_type: SERIAL_IO_MEM },
#define SERIAL_PORT_DFNS \
STD_SERIAL_PORT_DFNS
#endif /* __ASMPPC_SPRUCE_SERIAL_H */
......@@ -151,7 +151,7 @@ void
gen550_init(int i, struct uart_port *serial_req)
{
rs_table[i].io_type = serial_req->iotype;
rs_table[i].port = serial_req->line;
rs_table[i].port = serial_req->iobase;
rs_table[i].iomem_base = serial_req->membase;
rs_table[i].iomem_reg_shift = serial_req->regshift;
}
......
......@@ -21,6 +21,12 @@
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#ifdef CONFIG_PPC_INDIRECT_PCI_BE
#define PCI_CFG_OUT out_be32
#else
#define PCI_CFG_OUT out_le32
#endif
static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
......@@ -37,9 +43,10 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
if (bus->number != hose->first_busno)
cfg_type = 1;
out_be32(hose->cfg_addr,
(((offset & 0xfc) | cfg_type) << 24) | (devfn << 16)
| ((bus->number - hose->bus_offset) << 8) | 0x80);
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | ((dev->bus->number - hose->bus_offset) << 16)
| (dev->devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
......@@ -75,9 +82,10 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
if (bus->number != hose->first_busno)
cfg_type = 1;
out_be32(hose->cfg_addr,
(((offset & 0xfc) | cfg_type) << 24) | (devfn << 16)
| ((bus->number - hose->bus_offset) << 8) | 0x80);
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | ((dev->bus->number - hose->bus_offset) << 16)
| (dev->devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
......
......@@ -21,7 +21,7 @@
#include <asm/pci.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
/*
* The Falcon/Raven and HAWK has 4 sets of registers:
......@@ -95,10 +95,10 @@ pplus_init(struct pci_controller *hose,
/*
* Disable previous PPC->PCI mappings.
*/
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
/*
* Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
......@@ -113,21 +113,23 @@ pplus_init(struct pci_controller *hose,
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
/* Set up PPC->MPIC mapping on the bridge */
addr = processor_mpic_base |
(((processor_mpic_base + PPLUS_MPIC_SIZE) >> 16) - 1);
offset = 0xc2; /* No write posting for this PCI Mem space */
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), offset);
(((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
/* No write posting for this PCI Mem space */
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
(processor_pci_io_end - processor_pci_io_start + 1));
......@@ -137,8 +139,8 @@ pplus_init(struct pci_controller *hose,
* The PCI config addr/data pair based on start addr of PCI I/O space.
*/
setup_indirect_pci(hose,
processor_pci_io_start + PPLUS_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + PPLUS_PCI_CONFIG_DATA_OFF);
processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
/*
* Disable previous PCI->PPC mappings.
......@@ -161,10 +163,12 @@ pplus_init(struct pci_controller *hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_1,
processor_mpic_base | 0x0);
(processor_mpic_base -
processor_pci_mem_start +
hose->mem_space.start) | 0x0);
/* Map MPIC into vitual memory */
OpenPIC_Addr = ioremap(processor_mpic_base, PPLUS_MPIC_SIZE);
OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
return 0;
}
......@@ -181,14 +185,14 @@ pplus_init(struct pci_controller *hose,
#define MB (1024*1024)
static uint reg_offset_table[] __initdata = {
PPLUS_SMC_RAM_A_SIZE_REG_OFF,
PPLUS_SMC_RAM_B_SIZE_REG_OFF,
PPLUS_SMC_RAM_C_SIZE_REG_OFF,
PPLUS_SMC_RAM_D_SIZE_REG_OFF,
PPLUS_SMC_RAM_E_SIZE_REG_OFF,
PPLUS_SMC_RAM_F_SIZE_REG_OFF,
PPLUS_SMC_RAM_G_SIZE_REG_OFF,
PPLUS_SMC_RAM_H_SIZE_REG_OFF
HAWK_SMC_RAM_A_SIZE_REG_OFF,
HAWK_SMC_RAM_B_SIZE_REG_OFF,
HAWK_SMC_RAM_C_SIZE_REG_OFF,
HAWK_SMC_RAM_D_SIZE_REG_OFF,
HAWK_SMC_RAM_E_SIZE_REG_OFF,
HAWK_SMC_RAM_F_SIZE_REG_OFF,
HAWK_SMC_RAM_G_SIZE_REG_OFF,
HAWK_SMC_RAM_H_SIZE_REG_OFF
};
static uint falcon_size_table[] __initdata = {
......@@ -246,13 +250,13 @@ pplus_get_mem_size(uint smc_base)
size_table_entries = sizeof(falcon_size_table) /
sizeof(falcon_size_table[0]);
reg_limit = PPLUS_FALCON_SMC_REG_COUNT;
reg_limit = FALCON_SMC_REG_COUNT;
}
else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
size_table = hawk_size_table;
size_table_entries = sizeof(hawk_size_table) /
sizeof(hawk_size_table[0]);
reg_limit = PPLUS_HAWK_SMC_REG_COUNT;
reg_limit = HAWK_SMC_REG_COUNT;
}
else {
printk("pplus_get_mem_size: %s (0x%x)\n",
......
This diff is collapsed.
#include <asm-generic/dma-mapping.h>
/*
* This is based on both include/asm-sh/dma-mapping.h and
* include/asm-ppc/pci.h
*/
#ifndef __ASM_PPC_DMA_MAPPING_H
#define __ASM_PPC_DMA_MAPPING_H
#include <linux/config.h>
/* we implement the API below in terms of the existing PCI one,
* so include it */
#include <linux/pci.h>
/* need struct page definitions */
#include <linux/mm.h>
#include <linux/device.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#define dma_supported(dev, mask) (1)
static inline int dma_set_mask(struct device *dev, u64 dma_mask)
{
if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = dma_mask;
return 0;
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, int flag)
{
#ifdef CONFIG_PCI
if (dev && dev->bus == &pci_bus_type)
return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
#endif
return consistent_alloc(flag, size, dma_handle);
}
static inline void
dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
#ifdef CONFIG_PCI
if (dev && dev->bus == &pci_bus_type) {
pci_free_consistent(to_pci_dev(dev), size, vaddr, dma_handle);
return;
}
#endif
consistent_free(vaddr);
}
static inline dma_addr_t
dma_map_single(struct device *dev, void *ptr, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync(ptr, size, direction);
return virt_to_bus(ptr);
}
/* We do nothing. */
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline dma_addr_t
dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync_page(page, offset, size, direction);
return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
}
/* We do nothing. */
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline int
dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++) {
BUG_ON(!sg->page);
consistent_sync_page(sg->page, sg->offset,
sg->length, direction);
sg->dma_address = page_to_bus(sg->page) + sg->offset;
}
return nents;
}
/* We don't do anything here. */
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync(bus_to_virt(dma_handle), size, direction);
}
static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nelems; i++, sg++)
consistent_sync_page(sg->page, sg->offset,
sg->length, direction);
}
/* Now for the API extensions over the pci_ one */
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_is_consistent(d) (1)
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline void
dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything, that's all the pci API can do */
dma_sync_single(dev, dma_handle, offset + size, direction);
}
static inline void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction direction)
{
consistent_sync(vaddr, size, (int)direction);
}
#endif /* __ASM_PPC_DMA_MAPPING_H */
/*
* include/asm-ppc/hawk.h
*
* Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_H
#define __ASMPPC_HAWK_H
#include <asm/pci-bridge.h>
#include <asm/hawk_defs.h>
extern int hawk_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
/*
* include/asm-ppc/pplus.h
* include/asm-ppc/hawk_defs.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_PPLUS_H
#define __ASMPPC_PPLUS_H
#ifndef __ASMPPC_HAWK_DEFS_H
#define __ASMPPC_HAWK_DEFS_H
#include <asm/pci-bridge.h>
......@@ -27,66 +29,48 @@
* 4) System Memory Controller (SMC) registers.
*/
#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057
#define PPLUS_HAWK_VEND_DEV_ID 0x48031057
#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc
#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc
#define PPLUS_MPIC_SIZE 0x00040000U
#define PPLUS_SMC_SIZE 0x00001000U
#define HAWK_MPIC_SIZE 0x00040000U
#define HAWK_SMC_SIZE 0x00001000U
/*
* Define PPC register offsets.
*/
#define PPLUS_PPC_XSADD0_OFF 0x40
#define PPLUS_PPC_XSOFF0_OFF 0x44
#define PPLUS_PPC_XSADD1_OFF 0x48
#define PPLUS_PPC_XSOFF1_OFF 0x4c
#define PPLUS_PPC_XSADD2_OFF 0x50
#define PPLUS_PPC_XSOFF2_OFF 0x54
#define PPLUS_PPC_XSADD3_OFF 0x58
#define PPLUS_PPC_XSOFF3_OFF 0x5c
#define HAWK_PPC_XSADD0_OFF 0x40
#define HAWK_PPC_XSOFF0_OFF 0x44
#define HAWK_PPC_XSADD1_OFF 0x48
#define HAWK_PPC_XSOFF1_OFF 0x4c
#define HAWK_PPC_XSADD2_OFF 0x50
#define HAWK_PPC_XSOFF2_OFF 0x54
#define HAWK_PPC_XSADD3_OFF 0x58
#define HAWK_PPC_XSOFF3_OFF 0x5c
/*
* Define PCI register offsets.
*/
#define PPLUS_PCI_PSADD0_OFF 0x80
#define PPLUS_PCI_PSOFF0_OFF 0x84
#define PPLUS_PCI_PSADD1_OFF 0x88
#define PPLUS_PCI_PSOFF1_OFF 0x8c
#define PPLUS_PCI_PSADD2_OFF 0x90
#define PPLUS_PCI_PSOFF2_OFF 0x94
#define PPLUS_PCI_PSADD3_OFF 0x98
#define PPLUS_PCI_PSOFF3_OFF 0x9c
#define HAWK_PCI_PSADD0_OFF 0x80
#define HAWK_PCI_PSOFF0_OFF 0x84
#define HAWK_PCI_PSADD1_OFF 0x88
#define HAWK_PCI_PSOFF1_OFF 0x8c
#define HAWK_PCI_PSADD2_OFF 0x90
#define HAWK_PCI_PSOFF2_OFF 0x94
#define HAWK_PCI_PSADD3_OFF 0x98
#define HAWK_PCI_PSOFF3_OFF 0x9c
/*
* Define the System Memory Controller (SMC) register offsets.
*/
#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10
#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11
#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12
#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13
#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define PPLUS_FALCON_SMC_REG_COUNT 4
#define PPLUS_HAWK_SMC_REG_COUNT 8
int pplus_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base);
unsigned long pplus_get_mem_size(uint smc_base);
int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10
#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11
#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12
#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13
#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define FALCON_SMC_REG_COUNT 4
#define HAWK_SMC_REG_COUNT 8
#endif /* __ASMPPC_HAWK_DEFS_H */
......@@ -82,7 +82,6 @@ extern unsigned long pci_dram_offset;
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#ifdef CONFIG_PPC_PMAC
/*
* On powermacs, we will get a machine check exception if we
* try to read data from a non-existent I/O port. Because the
......@@ -94,7 +93,7 @@ extern unsigned long pci_dram_offset;
* all PPC implementations tested so far. The twi and isync are
* needed on the 601 (in fact twi; sync works too), the isync and
* nop are needed on 604[e|r], and any of twi, sync or isync will
* work on 603[e], 750, 74x0.
* work on 603[e], 750, 74xx.
* The twi creates an explicit data dependency on the returned
* value which seems to be needed to make the 601 wait for the
* load to finish.
......@@ -140,27 +139,17 @@ extern __inline__ void name(unsigned int val, unsigned int port) \
}
__do_in_asm(inb, "lbzx")
__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
__do_in_asm(inw, "lhz%U1%X1")
__do_in_asm(inl, "lwz%U1%X1")
__do_out_asm(outl,"stw%U0%X0")
__do_out_asm(outw, "sth%U0%X0")
#else
__do_in_asm(inw, "lhbrx")
__do_in_asm(inl, "lwbrx")
__do_out_asm(outb, "stbx")
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")
#elif defined(CONFIG_APUS)
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else /* not APUS or PMAC */
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
#define inb_p(port) inb((port))
......@@ -291,12 +280,19 @@ extern inline void eieio(void)
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(volatile unsigned char *addr)
{
int ret;
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__(
"lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -309,7 +305,9 @@ extern inline int in_le16(volatile unsigned short *addr)
{
int ret;
__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
__asm__ __volatile__("lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
......@@ -318,7 +316,9 @@ extern inline int in_be16(volatile unsigned short *addr)
{
int ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -337,7 +337,9 @@ extern inline unsigned in_le32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
......@@ -346,7 +348,9 @@ extern inline unsigned in_be32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -417,7 +421,7 @@ extern void consistent_sync_page(struct page *page, unsigned long offset,
#define dma_cache_wback_inv(_start,_size) do { } while (0)
#define consistent_alloc(gfp, size, handle) NULL
#define consistent_free(addr, size) do { } while (0)
#define consistent_free(addr) do { } while (0)
#define consistent_sync(addr, size, rw) do { } while (0)
#define consistent_sync_page(pg, off, sz, rw) do { } while (0)
......
......@@ -43,6 +43,8 @@ struct machdep_calls {
long (*time_init)(void); /* Optional, may be NULL */
int (*set_rtc_time)(unsigned long nowtime);
unsigned long (*get_rtc_time)(void);
unsigned char (*rtc_read_val)(int addr);
void (*rtc_write_val)(int addr, unsigned char val);
void (*calibrate_decr)(void);
void (*heartbeat)(void);
......
......@@ -27,7 +27,7 @@
#elif defined(CONFIG_SANDPOINT)
#include <platforms/sandpoint.h>
#elif defined(CONFIG_SPRUCE)
#include <platforms/spruce_serial.h>
#include <platforms/spruce.h>
#elif defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#else
......
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