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Commit 92c06c66 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://ppc.bkbits.net/for-linus-ppc 

into ppc970.osdl.org:/home/torvalds/v2.5/linux
parents 2c4dcfb7 bbb760e0
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Showing with 2186 additions and 1335 deletions
arch/ppc/Kconfig
View file @ 92c06c66
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS
default y
config FORCE
......
arch/ppc/boot/Makefile
View file @ 92c06c66
......@@ -16,13 +16,12 @@ HOSTCFLAGS += -Iarch/$(ARCH)/boot/include
BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd
bootdir-y := simple
bootdir-$(CONFIG_PPC_OF) := openfirmware
bootdir-$(CONFIG_PPC_PREP) += prep
bootdir-$(CONFIG_PPC_OF) += openfirmware
subdir-y := lib/ common/ images/
subdir-$(CONFIG_PPC_OF) += of1275/
# for cleaning
subdir- += simple/ openfirmware/ prep/
subdir- += simple/ openfirmware/
host-progs := $(addprefix utils/, addnote mknote hack-coff mkprep mkbugboot mktree)
......
arch/ppc/boot/common/Makefile
View file @ 92c06c66
......@@ -9,8 +9,5 @@
#
lib-y := string.o util.o misc-common.o \
serial_stub.o
lib-$(CONFIG_PPC_PREP) += mpc10x_memory.o
lib-$(CONFIG_LOPEC) += mpc10x_memory.o
lib-$(CONFIG_PAL4) += cpc700_memory.o
serial_stub.o bootinfo.o
lib-$(CONFIG_SERIAL_8250_CONSOLE) += ns16550.o
arch/ppc/boot/common/util.S
View file @ 92c06c66
......@@ -14,7 +14,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -36,6 +36,13 @@ disable_6xx_mmu:
*/
li r8,MSR_IP|MSR_FP
mtmsr r8
isync
/* Test for a 601 */
mfpvr r10
srwi r10,r10,16
cmpi 0,r10,1 /* 601 ? */
beq .clearbats_601
/* Clear BATs */
li r8,0
......@@ -47,6 +54,7 @@ disable_6xx_mmu:
mtspr DBAT2L,r8
mtspr DBAT3U,r8
mtspr DBAT3L,r8
.clearbats_601:
mtspr IBAT0U,r8
mtspr IBAT0L,r8
mtspr IBAT1U,r8
......@@ -68,6 +76,7 @@ disable_6xx_mmu:
addi r8,r8,0x111 /* increment VSID */
addis r10,r10,0x1000 /* address of next segment */
bdnz 3b
blr
.globl disable_6xx_l1cache
disable_6xx_l1cache:
......
arch/ppc/boot/lib/Makefile
View file @ 92c06c66
......@@ -2,4 +2,7 @@
# Makefile for some libs needed by zImage.
#
CFLAGS_kbd.o += -Idrivers/char
lib-y := zlib.o div64.o
lib-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o
arch/ppc/boot/openfirmware/Makefile
View file @ 92c06c66
......@@ -162,7 +162,7 @@ zImage.initrd: $(images)/vmlinux.initrd.coff \
$(images)/miboot.initrd.image
@echo ' kernel: $@ is ready ($<)'
TFTPIMAGE := /tftpboot/zImage.
TFTPIMAGE := /tftpboot/zImage
.PHONY: znetboot znetboot.initrd
znetboot: $(images)/vmlinux.coff \
......
arch/ppc/boot/prep/Makefile deleted 100644 → 0
View file @ 2c4dcfb7
# arch/ppc/boot/Makefile
#
# This file is subject to the terms and conditions of the GNU General Public
# License. See the file "COPYING" in the main directory of this archive
# for more details.
#
# Tom Rini January 2001
#
# Originally:
# arch/ppc/boot/Makefile
# Copyright (C) 1994 by Linus Torvalds
# Adapted for PowerPC by Gary Thomas
# modified by Cort (cort@cs.nmt.edu)
#
TFTPIMAGE := /tftpboot/zImage.prep
ifeq ($(CONFIG_SMP),y)
TFTPIMAGE := $(TFTPIMAGE).smp
endif
boot-y := head.o misc.o
boot-$(CONFIG_VGA_CONSOLE) += vreset.o kbd.o
boot := arch/ppc/boot
common := $(boot)/common
utils := $(boot)/utils
bootlib := $(boot)/lib
images := $(boot)/images
simple := $(boot)/simple
of1275 := $(boot)/of1275
OBJCOPYFLAGS := -O elf32-powerpc
LIBS := $(common)/lib.a $(bootlib)/lib.a $(of1275)/lib.a
targets := $(boot-y) dummy.o ../simple/legacy.o
OBJS := $(addprefix $(obj)/,$(boot-y)) $(simple)/legacy.o
# Extra include search dirs
CFLAGS_kbd.o += -Idrivers/char
zImage: initrd :=
zImage: $(images)/zImage.prep
@echo ' kernel: $@ is ready ($<)'
zImage.initrd: initrd := .initrd
zImage.initrd: $(images)/zImage.initrd.prep
@echo ' kernel: $@ is ready ($<)'
$(images)/ramdisk.image.gz:
@echo ' MISSING $@'
@echo ' RAM disk image must be provided separately'
@/bin/false
OBJCOPYFLAGS_image.o := \
--add-section=.image=$(images)/vmlinux.gz \
--set-section-flags=.image=contents,alloc,load,readonly,data
targets += image.o
$(obj)/image.o: $(obj)/dummy.o $(images)/vmlinux.gz
$(call if_changed,objcopy)
OBJCOPYFLAGS_image.initrd.o := \
--add-section=.ramdisk=$(images)/ramdisk.image.gz \
--set-section-flags=.ramdisk=contents,alloc,load,readonly,data \
--add-section=.image=$(images)/vmlinux.gz \
--set-section-flags=.image=contents,alloc,load,readonly,data
targets += image.initrd.o
$(obj)/image.initrd.o: $(obj)/dummy.o $(images)/vmlinux.gz $(images)/ramdisk.image.gz
$(call if_changed,objcopy)
LDFLAGS_zImage.bin := -Ttext 0x00800000 -Bstatic -T
LDFLAGS_zImage.initrd.bin := -Ttext 0x00800000 -Bstatic -T
targets += zImage.bin
$(obj)/zImage.bin: $(boot)/ld.script $(OBJS) $(obj)/image.o $(LIBS)
$(call if_changed,ld)
targets += zImage.initrd.bin
$(obj)/zImage.initrd.bin: $(boot)/ld.script $(OBJS) $(obj)/image.initrd.o $(LIBS)
$(call if_changed,ld)
OBJCOPYFLAGS_zImage := -R .comment -R .stab -R .stabstr
OBJCOPYFLAGS_zImage.initrd := -R .comment -R .stab -R .stabstr
targets += zImage
$(obj)/zImage: %: %.bin FORCE
$(call if_changed,objcopy)
targets += zImage.initrd
$(obj)/zImage.initrd: %: %.bin FORCE
$(call if_changed,objcopy)
quiet_cmd_mkprep = MKPREP $@
cmd_mkprep = $(utils)/mkprep -pbp $< $@
$(images)/zImage.prep: $(obj)/zImage $(utils)/mkprep
$(call cmd,mkprep)
$(images)/zImage.initrd.prep: $(obj)/zImage.initrd $(utils)/mkprep
$(call cmd,mkprep)
#
# Convinient shorthands for various targets
#
floppy: zImage
dd if=$(images)/zImage.prep of=/dev/fd0H1440 bs=64b
znetboot : zImage
cp $(images)/zImage.prep $(TFTPIMAGE)
@echo ' kernel: $@ is ready ($<)'
znetboot.initrd : zImage.initrd
cp $(images)/zImage.initrd.prep $(TFTPIMAGE)
@echo ' kernel: $@ is ready ($<)'
arch/ppc/boot/prep/dummy.c deleted 100644 → 0
View file @ 2c4dcfb7
int main(void)
{
return 0;
}
arch/ppc/boot/prep/head.S deleted 100644 → 0
View file @ 2c4dcfb7
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include <asm/cache.h>
.text
/*
* Boot loader philosophy:
* ROM loads us to some arbitrary location
* Move the boot code to the link address (8M)
* Call decompress_kernel()
* Relocate the initrd, zimage and residual data to 8M
* Decompress the kernel to 0
* Jump to the kernel entry
* -- Cort
*/
.globl start
start:
bl start_
start_:
/* Enable, invalidate, Disable L1 icache/dcache */
li r8, 0
ori r8, r8, (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
mfspr r11,HID0
or r11,r11,r8
andc r10,r11,r8
isync
mtspr HID0,r8
sync
isync
mtspr HID0,r10
sync
isync
mr r11,r3 /* Save pointer to residual/board data */
/*
* Save the OF pointer to r25, but only if the entry point is in a sane
* location; if not we store 0. If there is no entry point, or it is
* invalid, we establish the default MSR value immediately. Otherwise,
* we defer doing that, to allow OF functions to be called, until we
* begin uncompressing the kernel.
*/
lis r3,0x0fff /* r3 = 0x0fffffff */
ori r3,r3,0xffff
subc r3,r3,r5 /* r3 = (r5 <= r3) ? ~0 : 0 */
subfe r3,r3,r3
nand r3,r3,r3
and. r5,r5,r3 /* r5 will be cleared if (r5 > r3) */
bne+ haveOF
li r3,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
mtmsr r3
isync
haveOF:
mr r25,r5
/* compute the size of the whole image in words. */
lis r4,start@h
ori r4,r4,start@l
lis r5,end@h
ori r5,r5,end@l
addi r5,r5,3 /* round up */
sub r5,r5,r4 /* end - start */
srwi r5,r5,2
mr r7,r5 /* Save for later use. */
/* check if we need to relocate ourselves to the link addr or were
* we loaded there to begin with -- Cort */
mflr r3
subi r3,r3,4 /* we get the nip, not the ip of the branch */
mr r8,r3
cmp 0,r3,r4
beq start_ldr /* If 0, we don't need to relocate */
/*
* no matter where we're loaded, move ourselves to -Ttext address
*/
relocate:
mflr r3 /* Compute code bias */
subi r3,r3,4
mr r8,r3
lis r4,start@h
ori r4,r4,start@l
mr r5,r7 /* Get the # of longwords again */
mtctr r5 /* Setup for loop */
li r6,0
subi r3,r3,4
subi r4,r4,4
00: lwzu r5,4(r3)
stwu r5,4(r4)
xor r6,r6,r5
bdnz 00b
lis r3,start_ldr@h
ori r3,r3,start_ldr@l
mtlr r3 /* Easiest way to do an absolute jump */
blr
start_ldr:
/* Some boards don't boot up with the I-cache enabled. Do that
* now because the decompress runs much faster that way.
* As a side effect, we have to ensure the data cache is not enabled
* so we can access the serial I/O without trouble.
*/
bl flush_instruction_cache
/* Clear all of BSS */
lis r3,edata@h
ori r3,r3,edata@l
lis r4,end@h
ori r4,r4,end@l
subi r3,r3,4
subi r4,r4,4
li r0,0
50: stwu r0,4(r3)
cmp 0,r3,r4
bne 50b
90: mr r9,r1 /* Save old stack pointer (in case it matters) */
lis r1,.stack@h
ori r1,r1,.stack@l
addi r1,r1,4096*2
subi r1,r1,256
li r2,0x000F /* Mask pointer to 16-byte boundary */
andc r1,r1,r2
/* Run loader */
mr r3,r8 /* Load point */
mr r4,r7 /* Program length */
mr r5,r6 /* Checksum */
mr r6,r11 /* Residual data */
mr r7,r25 /* Validated OFW interface */
bl decompress_kernel
/*
* We have to do this after decompress_kernel, just to make
* sure we don't wipe out things mapped in BATs which we need.
* -- Tom
*/
li r6,0
/* Test for a 601 */
mfspr r9,PVR
srwi r9,r9,16
cmpi 0,r9,1 /* 601 ? */
beq .clearbats_601
/* Clear BATS */
mtspr DBAT0U,r6
mtspr DBAT0L,r6
mtspr DBAT1U,r6
mtspr DBAT1L,r6
mtspr DBAT2U,r6
mtspr DBAT2L,r6
mtspr DBAT3U,r6
mtspr DBAT3L,r6
.clearbats_601:
mtspr IBAT0U,r6
mtspr IBAT0L,r6
mtspr IBAT1U,r6
mtspr IBAT1L,r6
mtspr IBAT2U,r6
mtspr IBAT2L,r6
mtspr IBAT3U,r6
mtspr IBAT3L,r6
isync
sync
sync
/* Set segment registers */
li r6,16 /* load up segment register values */
mtctr r6 /* for context 0 */
lis r6,0x2000 /* Ku = 1, VSID = 0 */
li r10,0
3: mtsrin r6,r10
addi r6,r6,0x111 /* increment VSID */
addis r10,r10,0x1000 /* address of next segment */
bdnz 3b
/* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
* and tell the kernel to start on the 4th instruction since we
* overwrite the first 3 sometimes (which are 'nop').
*/
li r9,0xc
mtlr r9
lis r10,0xdeadc0de@h
ori r10,r10,0xdeadc0de@l
li r9,0
stw r10,0(r9)
blr
.comm .stack,4096*2,4
arch/ppc/boot/simple/Makefile
View file @ 92c06c66
......@@ -26,11 +26,12 @@ common := $(boot)/common
utils := $(boot)/utils
bootlib := $(boot)/lib
images := $(boot)/images
of1275 := $(boot)/of1275
tftpboot := /tftpboot
# Normally, we use the 'misc.c' file for decompress_kernel and
# whatnot. Sometimes we need to override this however.
misc-y := misc.o ../common/bootinfo.o
misc-y := misc.o
# Normally, we have our images end in .elf, but something we want to
# change this.
......@@ -89,6 +90,7 @@ zimageinitrd-$(motorola) := zImage.initrd-PPLUS
# Overrides previous assingment
extra.o-$(CONFIG_PPLUS) := legacy.o
extra.o-$(CONFIG_LOPEC) := mpc10x_memory.o
zimage-$(pcore) := zImage-STRIPELF
zimageinitrd-$(pcore) := zImage.initrd-STRIPELF
......@@ -96,6 +98,12 @@ zimageinitrd-$(pcore) := zImage.initrd-STRIPELF
end-$(pcore) := pcore
cacheflag-$(pcore) := -include $(clear_L2_L3)
zimage-$(CONFIG_PPC_PREP) := zImage-PPLUS
zimageinitrd-$(CONFIG_PPC_PREP) := zImage.initrd-PPLUS
extra.o-$(CONFIG_PPC_PREP) := legacy.o
misc-$(CONFIG_PPC_PREP) += misc-prep.o mpc10x_memory.o
end-$(CONFIG_PPC_PREP) := prep
end-$(CONFIG_SANDPOINT) := sandpoint
cacheflag-$(CONFIG_SANDPOINT) := -include $(clear_L2_L3)
......@@ -138,6 +146,9 @@ boot-$(CONFIG_GT64260_CONSOLE) += gt64260_tty.o
endif
LIBS := $(common)/lib.a $(bootlib)/lib.a
ifeq ($(CONFIG_PPC_PREP),y)
LIBS += $(of1275)/lib.a
endif
OBJS := $(addprefix $(obj)/,$(boot-y))
......@@ -199,10 +210,10 @@ $(images)/zImage.initrd-TREE: $(obj)/zvmlinux.initrd $(MKTREE)
$(MKTREE) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y) \
$(ENTRYPOINT)
$(images)/zImage-PPLUS: $(obj)/zvmlinux $(MKPREP) $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.pplus
$(images)/zImage-PPLUS: $(obj)/zvmlinux $(utils)/mkprep $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux $(images)/zImage.$(end-y)
$(MKBUGBOOT) $(obj)/zvmlinux $(images)/zImage.bugboot
$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(MKPREP) $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.pplus
$(images)/zImage.initrd-PPLUS: $(obj)/zvmlinux.initrd $(utils)/mkprep $(MKBUGBOOT)
$(MKPREP) -pbp $(obj)/zvmlinux.initrd $(images)/zImage.initrd.$(end-y)
$(MKBUGBOOT) $(obj)/zvmlinux.initrd $(images)/zImage.initrd.bugboot
arch/ppc/boot/simple/head.S
View file @ 92c06c66
......@@ -7,7 +7,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2003 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -57,10 +57,11 @@ start_:
isync
#endif
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6)
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
mr r29,r3 /* On the MBX860, r3 is the board info pointer.
* On the RPXSUPER, r3 points to the
* NVRAM configuration keys.
* On the RPXSUPER, r3 points to the NVRAM
* configuration keys.
* On PReP, r3 is the pointer to the residual data.
*/
#endif
......@@ -69,7 +70,36 @@ start_:
/* The following functions we call must not modify r3 or r4.....
*/
#ifdef CONFIG_6xx
/* On PReP we must look at the OpenFirmware pointer and sanity
* test it. On other platforms, we disable the MMU right now
* and other bits.
*/
#ifdef CONFIG_PPC_PREP
/*
* Save the OF pointer to r25, but only if the entry point is in a sane
* location; if not we store 0. If there is no entry point, or it is
* invalid, we establish the default MSR value immediately. Otherwise,
* we defer doing that, to allow OF functions to be called, until we
* begin uncompressing the kernel.
*/
lis r8,0x0fff /* r8 = 0x0fffffff */
ori r8,r8,0xffff
subc r8,r8,r5 /* r8 = (r5 <= r8) ? ~0 : 0 */
subfe r8,r8,r8
nand r8,r8,r8
and. r5,r5,r8 /* r5 will be cleared if (r5 > r8) */
bne+ haveOF
li r8,MSR_IP|MSR_FP /* Not OF: set MSR immediately */
mtmsr r8
isync
haveOF:
mr r25,r5
#else
bl disable_6xx_mmu
#endif
bl disable_6xx_l1cache
CLEAR_CACHES
......@@ -99,7 +129,7 @@ start_:
mr r3, r29
#endif
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6)
#if defined(CONFIG_MBX) || defined(CONFIG_RPX6) || defined(CONFIG_PPC_PREP)
mr r4,r29 /* put the board info pointer where the relocate
* routine will find it
*/
......
arch/ppc/boot/prep/misc.c → arch/ppc/boot/simple/misc-prep.c
View file @ 92c06c66
/*
* arch/ppc/boot/prep/misc.c
* arch/ppc/boot/simple/misc-prep.c
*
* Adapted for PowerPC by Gary Thomas
* Maintainer: Tom Rini <trini@kernel.crashing.org>
*
* Rewritten by Cort Dougan (cort@cs.nmt.edu)
* One day to be replaced by a single bootloader for chrp/prep/pmac. -- Cort
* In the past: Gary Thomas, Cort Dougan <cort@cs.nmt.edu>
*/
#include <linux/types.h>
#include <linux/string.h>
#include <asm/residual.h>
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/elf.h>
#include <linux/pci_ids.h>
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/bootinfo.h>
#include <asm/mmu.h>
#include <linux/types.h>
#include <asm/residual.h>
#include <asm/string.h>
#include <asm/byteorder.h>
#include "mpc10x.h"
#include "of1275.h"
#include "nonstdio.h"
#include "zlib.h"
/*
* Please send me load/board info and such data for hardware not
* listed here so I can keep track since things are getting tricky
* with the different load addrs with different firmware. This will
* help to avoid breaking the load/boot process.
* -- Cort
*/
char *avail_ram;
char *end_avail;
/* The linker tells us where the image is. */
extern char __image_begin, __image_end;
extern char __ramdisk_begin, __ramdisk_end;
extern char _end[];
#ifdef CONFIG_CMDLINE
#define CMDLINE CONFIG_CMDLINE
#else
#define CMDLINE ""
#endif
char cmd_preset[] = CMDLINE;
char cmd_buf[256];
char *cmd_line = cmd_buf;
int keyb_present = 1; /* keyboard controller is present by default */
extern int keyb_present; /* keyboard controller is present by default */
RESIDUAL hold_resid_buf;
RESIDUAL *hold_residual = &hold_resid_buf;
unsigned long initrd_size = 0;
char *zimage_start;
int zimage_size;
static void *OFW_interface; /* Pointer to OF, if available. */
#if defined(CONFIG_SERIAL_8250_CONSOLE)
unsigned long com_port;
#endif /* CONFIG_SERIAL_8250_CONSOLE */
#ifdef CONFIG_VGA_CONSOLE
char *vidmem = (char *)0xC00B8000;
int lines = 25, cols = 80;
......@@ -69,9 +32,12 @@ extern int vga_init(unsigned char *ISA_mem);
extern void gunzip(void *, int, unsigned char *, int *);
extern unsigned long serial_init(int chan, void *ignored);
extern void serial_fixups(void);
extern unsigned long get_mem_size(void);
extern struct bi_record *decompress_kernel(unsigned long load_addr,
int num_words, unsigned long cksum);
extern void disable_6xx_mmu(void);
extern unsigned long mpc10x_get_mem_size(void);
void
static void
writel(unsigned int val, unsigned int address)
{
/* Ensure I/O operations complete */
......@@ -79,24 +45,21 @@ writel(unsigned int val, unsigned int address)
*(unsigned int *)address = cpu_to_le32(val);
}
unsigned int
readl(unsigned int address)
{
/* Ensure I/O operations complete */
__asm__ volatile("eieio");
return le32_to_cpu(*(unsigned int *)address);
}
#define PCI_CFG_ADDR(dev,off) ((0x80<<24) | (dev<<8) | (off&0xfc))
#define PCI_CFG_DATA(off) (0x80000cfc+(off&3))
#define PCI_CFG_DATA(off) (MPC10X_MAPA_CNFG_DATA+(off&3))
static void
pci_read_config_32(unsigned char devfn,
unsigned char offset,
unsigned int *val)
{
writel(PCI_CFG_ADDR(devfn,offset), 0x80000cf8);
*val = readl(PCI_CFG_DATA(offset));
/* Ensure I/O operations complete */
__asm__ volatile("eieio");
*(unsigned int *)PCI_CFG_ADDR(devfn,offset) =
cpu_to_le32(MPC10X_MAPA_CNFG_ADDR);
/* Ensure I/O operations complete */
__asm__ volatile("eieio");
*val = le32_to_cpu(*(unsigned int *)PCI_CFG_DATA(offset));
return;
}
......@@ -113,60 +76,28 @@ scroll(void)
#endif /* CONFIG_VGA_CONSOLE */
unsigned long
decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
RESIDUAL *residual, void *OFW_interface)
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
RESIDUAL *residual, void *OFW)
{
int timer = 0;
extern unsigned long start;
char *cp, ch;
unsigned long TotalMemory;
int start_multi = 0;
unsigned int pci_viddid, pci_did, tulip_pci_base, tulip_base;
/* If we have Open Firmware, initialise it immediately */
if (OFW_interface)
if (OFW) {
OFW_interface = OFW;
ofinit(OFW_interface);
}
serial_fixups();
#if defined(CONFIG_SERIAL_8250_CONSOLE)
com_port = serial_init(0, NULL);
#endif /* CONFIG_SERIAL_8250_CONSOLE */
#if defined(CONFIG_VGA_CONSOLE)
vga_init((unsigned char *)0xC0000000);
#endif /* CONFIG_VGA_CONSOLE */
/*
* Tell the user where we were loaded at and where we were relocated
* to for debugging this process.
*/
puts("loaded at: "); puthex(load_addr);
puts(" "); puthex((unsigned long)(load_addr + (4*num_words))); puts("\n");
if ( (unsigned long)load_addr != (unsigned long)&start ) {
puts("relocated to: "); puthex((unsigned long)&start);
puts(" ");
puthex((unsigned long)((unsigned long)&start + (4*num_words)));
puts("\n");
}
if (residual) {
/*
* Tell the user where the residual data is.
*/
puts("board data at: "); puthex((unsigned long)residual);
puts(" ");
puthex((unsigned long)((unsigned long)residual +
sizeof(RESIDUAL)));
puts("\nrelocated to: ");puthex((unsigned long)hold_residual);
puts(" ");
puthex((unsigned long)((unsigned long)hold_residual +
sizeof(RESIDUAL)));
puts("\n");
/* Is this Motorola PPCBug? */
if ((1 & residual->VitalProductData.FirmwareSupports) &&
(1 == residual->VitalProductData.FirmwareSupplier)) {
unsigned char base_mod;
unsigned char board_type = inb(0x800) & 0xF0;
unsigned char board_type = inb(0x801) & 0xF0;
/*
* Reset the onboard 21x4x Ethernet
......@@ -209,11 +140,30 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
start_multi = 1;
}
memcpy(hold_residual,residual,sizeof(RESIDUAL));
} else {
/* Tell the user we didn't find anything. */
puts("No residual data found.\n");
}
/* Call decompress_kernel */
decompress_kernel(load_addr, num_words, cksum);
if (start_multi) {
residual->VitalProductData.SmpIar = (unsigned long)0xc0;
residual->Cpus[1].CpuState = CPU_GOOD;
hold_residual->VitalProductData.Reserved5 = 0xdeadbeef;
}
/* Now go and clear out the BATs and ensure that our MSR is
* correct .*/
disable_6xx_mmu();
/* Make r3 be a pointer to the residual data. */
return (unsigned long)hold_residual;
}
unsigned long
get_mem_size(void)
{
unsigned int pci_viddid, pci_did;
/* First, figure out what kind of host bridge we are on. If it's
* an MPC10x, we can ask it directly how much memory it has.
* Otherwise, see if the residual data has anything. This isn't
......@@ -228,10 +178,10 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
&& ((pci_did == PCI_DEVICE_ID_MOTOROLA_MPC105)
|| (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC106)
|| (pci_did == PCI_DEVICE_ID_MOTOROLA_MPC107)))
TotalMemory = get_mem_size();
return mpc10x_get_mem_size();
/* If it's not, see if we have anything in the residual data. */
else if (residual && residual->TotalMemory)
TotalMemory = residual->TotalMemory;
else if (hold_residual && hold_residual->TotalMemory)
return hold_residual->TotalMemory;
else if (OFW_interface) {
/*
* This is a 'best guess' check. We want to make sure
......@@ -252,174 +202,10 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
sizeof(mem_info)) != 8)
break;
TotalMemory = mem_info[1];
break;
}
} else
/* Fall back to hard-coding 32MB. */
TotalMemory = 32*1024*1024;
/* assume the chunk below 8M is free */
end_avail = (char *)0x00800000;
/*
* We link ourself to 0x00800000. When we run, we relocate
* ourselves there. So we just need __image_begin for the
* start. -- Tom
*/
zimage_start = (char *)(unsigned long)(&__image_begin);
zimage_size = (unsigned long)(&__image_end) -
(unsigned long)(&__image_begin);
initrd_size = (unsigned long)(&__ramdisk_end) -
(unsigned long)(&__ramdisk_begin);
/*
* The zImage and initrd will be between start and _end, so they've
* already been moved once. We're good to go now. -- Tom
*/
avail_ram = (char *)PAGE_ALIGN((unsigned long)_end);
puts("zimage at: "); puthex((unsigned long)zimage_start);
puts(" "); puthex((unsigned long)(zimage_size+zimage_start));
puts("\n");
if ( initrd_size ) {
puts("initrd at: ");
puthex((unsigned long)(&__ramdisk_begin));
puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n");
}
avail_ram = (char *)0x00400000;
end_avail = (char *)0x00800000;
puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" ");
puthex((unsigned long)end_avail); puts("\n");
if (keyb_present)
CRT_tstc(); /* Forces keyboard to be initialized */
puts("\nLinux/PPC load: ");
cp = cmd_line;
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
while ( *cp )
putc(*cp++);
while (timer++ < 5*1000) {
if (tstc()) {
while ((ch = getc()) != '\n' && ch != '\r') {
/* Test for backspace/delete */
if (ch == '\b' || ch == '\177') {
if (cp != cmd_line) {
cp--;
puts("\b \b");
}
/* Test for ^x/^u (and wipe the line) */
} else if (ch == '\030' || ch == '\025') {
while (cp != cmd_line) {
cp--;
puts("\b \b");
}
} else {
*cp++ = ch;
putc(ch);
}
}
break; /* Exit 'timer' loop */
}
udelay(1000); /* 1 msec */
}
*cp = 0;
puts("\nUncompressing Linux...");
/*
* If we have OF, then we have deferred setting the MSR.
* We must set it now because we are about to overwrite
* the exception table. The new MSR value will disable
* machine check exceptions and point the exception table
* to the ROM.
*/
if (OFW_interface) {
mtmsr(MSR_IP | MSR_FP);
asm volatile("isync");
}
gunzip(0, 0x400000, zimage_start, &zimage_size);
puts("done.\n");
if (start_multi) {
puts("Parking cpu1 at 0xc0\n");
residual->VitalProductData.SmpIar = (unsigned long)0xc0;
residual->Cpus[1].CpuState = CPU_GOOD;
hold_residual->VitalProductData.Reserved5 = 0xdeadbeef;
return mem_info[1];
}
{
struct bi_record *rec;
unsigned long initrd_loc;
unsigned long rec_loc = _ALIGN((unsigned long)(zimage_size) +
(1 << 20) - 1, (1 << 20));
rec = (struct bi_record *)rec_loc;
/* We need to make sure that the initrd and bi_recs do not
* overlap. */
if ( initrd_size ) {
initrd_loc = (unsigned long)(&__ramdisk_begin);
/* If the bi_recs are in the middle of the current
* initrd, move the initrd to the next MB
* boundary. */
if ((rec_loc > initrd_loc) &&
((initrd_loc + initrd_size)
> rec_loc)) {
initrd_loc = _ALIGN((unsigned long)(zimage_size)
+ (2 << 20) - 1, (2 << 20));
memmove((void *)initrd_loc, &__ramdisk_begin,
initrd_size);
puts("initrd moved: "); puthex(initrd_loc);
puts(" "); puthex(initrd_loc + initrd_size);
puts("\n");
}
}
rec->tag = BI_FIRST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_BOOTLOADER_ID;
memcpy( (void *)rec->data, "prepboot", 9);
rec->size = sizeof(struct bi_record) + 8 + 1;
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_MACHTYPE;
rec->data[0] = _MACH_prep;
rec->data[1] = 0;
rec->size = sizeof(struct bi_record) + 2 *
sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_MEMSIZE;
rec->data[0] = TotalMemory;
rec->size = sizeof(struct bi_record) + sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
rec->tag = BI_CMD_LINE;
memcpy( (char *)rec->data, cmd_line, strlen(cmd_line)+1);
rec->size = sizeof(struct bi_record) + strlen(cmd_line) + 1;
rec = (struct bi_record *)((unsigned long)rec + rec->size);
if ( initrd_size ) {
rec->tag = BI_INITRD;
rec->data[0] = initrd_loc;
rec->data[1] = initrd_size;
rec->size = sizeof(struct bi_record) + 2 *
sizeof(unsigned long);
rec = (struct bi_record *)((unsigned long)rec +
rec->size);
}
rec->tag = BI_LAST;
rec->size = sizeof(struct bi_record);
rec = (struct bi_record *)((unsigned long)rec + rec->size);
}
puts("Now booting the kernel\n");
return (unsigned long)hold_residual;
/* Fall back to hard-coding 32MB. */
return 32*1024*1024;
}
arch/ppc/boot/simple/misc-spruce.c
View file @ 92c06c66
......@@ -174,7 +174,8 @@ get_mem_size(void)
}
unsigned long
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
void *ign1, void *ign2)
{
int csr0;
int csr_id;
......
arch/ppc/boot/simple/misc.c
View file @ 92c06c66
......@@ -99,7 +99,9 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
unsigned long initrd_loc, TotalMemory = 0;
serial_fixups();
#ifdef CONFIG_SERIAL_8250_CONSOLE
com_port = serial_init(0, NULL);
#endif
#ifdef CONFIG_44x
/* Reset MAL */
......@@ -269,7 +271,8 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
/* Allow decompress_kernel to be hooked into. This is the default. */
void * __attribute__ ((weak))
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
void *ign1, void *ign2)
{
return decompress_kernel(load_addr, num_words, cksum);
}
arch/ppc/boot/common/mpc10x_memory.c → arch/ppc/boot/simple/mpc10x_memory.c
View file @ 92c06c66
......@@ -52,8 +52,12 @@ MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
* the system. This assumes that the firmware has correctly set up the memory
* controller registers. On CONFIG_PPC_PREP, we know we are being called
* under a PReP memory map. On all other machines, we assume we are under
* a CHRP memory map.
* a CHRP memory map. Further, on CONFIG_PPC_MULTIPLATFORM we must rename
* this function.
*/
#ifdef CONFIG_PPC_MULTIPLATFORM
#define get_mem_size mpc10x_get_mem_size
#endif
unsigned long
get_mem_size(void)
{
......
arch/ppc/boot/simple/relocate.S
View file @ 92c06c66
......@@ -9,7 +9,7 @@
* trini@mvista.com
* Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -101,8 +101,8 @@ relocate:
GETSYM(r4, __relocate_start)
GETSYM(r5, do_relocate)
sub r4,r5,r4 /* Get entry point for do_relocate in
add r6,r6,r4 * relocated section */
sub r4,r5,r4 /* Get entry point for do_relocate in */
add r6,r6,r4 /* relocated section */
/* This will return to the relocated do_relocate */
mtlr r6
......@@ -182,6 +182,7 @@ start_ldr:
mr r4,r7 /* Program length */
mr r5,r6 /* Checksum */
mr r6,r11 /* Residual data */
mr r7,r25 /* Validated OFW interface */
bl load_kernel
/*
......@@ -195,8 +196,18 @@ start_ldr:
/*
* Start at the begining.
*/
li r9,0x0000
li r9,0xc
mtlr r9
#ifdef CONFIG_PPC_MULTIPLATFORM
/* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
* and tell the kernel to start on the 4th instruction since we
* overwrite the first 3 sometimes (which are 'nop').
*/
lis r10,0xdeadc0de@h
ori r10,r10,0xdeadc0de@l
li r9,0
stw r10,0(r9)
#endif
blr
.comm .stack,4096*2,4
arch/ppc/configs/pplus_defconfig
View file @ 92c06c66
......@@ -4,11 +4,17 @@
CONFIG_MMU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_GENERIC_NVRAM=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_STANDALONE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
......@@ -18,9 +24,16 @@ CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
# CONFIG_HOTPLUG is not set
# CONFIG_IKCONFIG is not set
CONFIG_EMBEDDED=y
CONFIG_KALLSYMS=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
#
# Loadable module support
......@@ -33,24 +46,25 @@ CONFIG_OBSOLETE_MODPARM=y
CONFIG_KMOD=y
#
# Platform support
# Processor
#
CONFIG_PPC=y
CONFIG_PPC32=y
CONFIG_6xx=y
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_POWER3 is not set
# CONFIG_POWER4 is not set
# CONFIG_8xx is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
CONFIG_PPC_STD_MMU=y
#
# IBM 4xx options
# Platform options
#
# CONFIG_8260 is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PPC_STD_MMU=y
# CONFIG_PPC_MULTIPLATFORM is not set
# CONFIG_APUS is not set
# CONFIG_WILLOW_2 is not set
# CONFIG_WILLOW is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
# CONFIG_EV64260 is not set
......@@ -66,34 +80,29 @@ CONFIG_PPLUS=y
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
# CONFIG_EST8260 is not set
# CONFIG_SBS8260 is not set
# CONFIG_RPX6 is not set
# CONFIG_TQM8260 is not set
CONFIG_PPC_GEN550=y
# CONFIG_PPCBUG_NVRAM is not set
# CONFIG_SMP is not set
# CONFIG_PREEMPT is not set
# CONFIG_ALTIVEC is not set
# CONFIG_TAU is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_HIGHMEM is not set
CONFIG_KERNEL_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# General setup
# Bus options
#
# CONFIG_HIGHMEM is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_PCI_LEGACY_PROC is not set
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
CONFIG_PPC601_SYNC_FIX=y
# CONFIG_PPCBUG_NVRAM is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="ip=on"
#
# Advanced setup
......@@ -109,15 +118,27 @@ CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Device Drivers
#
#
# Generic Driver Options
#
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Block devices
......@@ -131,43 +152,42 @@ CONFIG_BLK_DEV_FD=y
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_LBD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# ATA/IDE/MFM/RLL support
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
#
# IDE, ATA and ATAPI Block devices
#
CONFIG_BLK_DEV_IDE=y
#
# Please see Documentation/ide.txt for help/info on IDE drives
#
# CONFIG_BLK_DEV_HD is not set
CONFIG_BLK_DEV_IDEDISK=y
# CONFIG_IDEDISK_MULTI_MODE is not set
# CONFIG_IDEDISK_STROKE is not set
CONFIG_BLK_DEV_IDECD=y
# CONFIG_BLK_DEV_IDETAPE is not set
CONFIG_BLK_DEV_IDEFLOPPY=y
CONFIG_BLK_DEV_IDESCSI=y
# CONFIG_IDE_TASK_IOCTL is not set
# CONFIG_IDE_TASKFILE_IO is not set
#
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=y
# CONFIG_BLK_DEV_IDEPCI is not set
# CONFIG_BLK_DEV_IDEDMA is not set
# CONFIG_IDEDMA_AUTO is not set
# CONFIG_DMA_NONPCI is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
# SCSI device support
#
CONFIG_SCSI=y
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
......@@ -196,11 +216,9 @@ CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
......@@ -208,39 +226,36 @@ CONFIG_SCSI_CONSTANTS=y
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_NCR53C8XX is not set
CONFIG_SCSI_SYM53C8XX=y
CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS=8
CONFIG_SCSI_NCR53C8XX_MAX_TAGS=32
CONFIG_SCSI_NCR53C8XX_SYNC=20
# CONFIG_SCSI_NCR53C8XX_PROFILE is not set
# CONFIG_SCSI_NCR53C8XX_IOMAPPED is not set
# CONFIG_SCSI_NCR53C8XX_PQS_PDS is not set
# CONFIG_SCSI_NCR53C8XX_SYMBIOS_COMPAT is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
CONFIG_SCSI_QLA2XXX=y
# CONFIG_SCSI_QLA21XX is not set
# CONFIG_SCSI_QLA22XX is not set
# CONFIG_SCSI_QLA2300 is not set
# CONFIG_SCSI_QLA2322 is not set
# CONFIG_SCSI_QLA6312 is not set
# CONFIG_SCSI_QLA6322 is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
# IEEE 1394 (FireWire) support
#
# CONFIG_IEEE1394 is not set
......@@ -249,6 +264,10 @@ CONFIG_SCSI_NCR53C8XX_SYNC=20
#
# CONFIG_I2O is not set
#
# Macintosh device drivers
#
#
# Networking support
#
......@@ -260,8 +279,6 @@ CONFIG_NET=y
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
# CONFIG_NETLINK_DEV is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
......@@ -281,6 +298,16 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
#
# IP: Virtual Server Configuration
#
# CONFIG_IP_VS is not set
# CONFIG_IPV6 is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
#
# IP: Netfilter Configuration
#
......@@ -292,11 +319,13 @@ CONFIG_IP_NF_FTP=m
# CONFIG_IP_NF_QUEUE is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_LIMIT=m
# CONFIG_IP_NF_MATCH_IPRANGE is not set
CONFIG_IP_NF_MATCH_MAC=m
CONFIG_IP_NF_MATCH_PKTTYPE=m
CONFIG_IP_NF_MATCH_MARK=m
CONFIG_IP_NF_MATCH_MULTIPORT=m
CONFIG_IP_NF_MATCH_TOS=m
# CONFIG_IP_NF_MATCH_RECENT is not set
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_DSCP=m
CONFIG_IP_NF_MATCH_AH_ESP=m
......@@ -306,15 +335,15 @@ CONFIG_IP_NF_MATCH_AH_ESP=m
CONFIG_IP_NF_MATCH_HELPER=m
CONFIG_IP_NF_MATCH_STATE=m
CONFIG_IP_NF_MATCH_CONNTRACK=m
CONFIG_IP_NF_MATCH_UNCLEAN=m
CONFIG_IP_NF_MATCH_OWNER=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_MIRROR=m
CONFIG_IP_NF_NAT=m
CONFIG_IP_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_REDIRECT=m
# CONFIG_IP_NF_TARGET_NETMAP is not set
# CONFIG_IP_NF_TARGET_SAME is not set
# CONFIG_IP_NF_NAT_LOCAL is not set
# CONFIG_IP_NF_NAT_SNMP_BASIC is not set
CONFIG_IP_NF_NAT_FTP=m
......@@ -324,10 +353,9 @@ CONFIG_IP_NF_TARGET_ULOG=m
# CONFIG_IP_NF_TARGET_TCPMSS is not set
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
# CONFIG_IP_NF_ARP_MANGLE is not set
CONFIG_IP_NF_COMPAT_IPCHAINS=m
# CONFIG_IP_NF_COMPAT_IPFWADM is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
......@@ -336,9 +364,9 @@ CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
......@@ -366,13 +394,13 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
CONFIG_CRC32=y
# CONFIG_OAKNET is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
......@@ -381,13 +409,22 @@ CONFIG_MII=y
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
CONFIG_NET_TULIP=y
# CONFIG_DE2104X is not set
CONFIG_TULIP=y
# CONFIG_TULIP_MWI is not set
# CONFIG_TULIP_MMIO is not set
# CONFIG_TULIP_NAPI is not set
# CONFIG_DE4X5 is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_DM9102 is not set
# CONFIG_HP100 is not set
CONFIG_NET_PCI=y
# CONFIG_PCNET32 is not set
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_FORCEDETH is not set
# CONFIG_DGRS is not set
CONFIG_EEPRO100=y
# CONFIG_EEPRO100_PIO is not set
......@@ -413,6 +450,7 @@ CONFIG_EEPRO100=y
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SIS190 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
......@@ -431,8 +469,9 @@ CONFIG_EEPRO100=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
# Token Ring devices
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -453,19 +492,19 @@ CONFIG_EEPRO100=y
# CONFIG_IRDA is not set
#
# ISDN subsystem
# Bluetooth support
#
# CONFIG_ISDN_BOOL is not set
# CONFIG_BT is not set
#
# Graphics support
# ISDN subsystem
#
# CONFIG_FB is not set
# CONFIG_ISDN is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
......@@ -482,18 +521,16 @@ CONFIG_EEPRO100=y
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
# CONFIG_SERIO is not set
# CONFIG_SERIO_I8042 is not set
#
# Input Device Drivers
#
#
# Macintosh device drivers
#
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
......@@ -501,6 +538,7 @@ CONFIG_SOUND_GAMEPORT=y
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=4
# CONFIG_SERIAL_8250_EXTENDED is not set
#
......@@ -509,26 +547,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
#
# Mice
#
CONFIG_BUSMOUSE=y
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
......@@ -554,7 +579,11 @@ CONFIG_GEN_RTC=y
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Multimedia devices
......@@ -566,6 +595,26 @@ CONFIG_GEN_RTC=y
#
# CONFIG_DVB is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# File systems
#
......@@ -600,10 +649,11 @@ CONFIG_ISO9660_FS=y
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
......@@ -628,6 +678,7 @@ CONFIG_RAMFS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
......@@ -638,7 +689,6 @@ CONFIG_SUNRPC=y
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
......@@ -648,31 +698,18 @@ CONFIG_SUNRPC=y
CONFIG_MSDOS_PARTITION=y
#
# Sound
# Native Language Support
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
# CONFIG_NLS is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
#
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_KALLSYMS is not set
# CONFIG_SERIAL_TEXT_DEBUG is not set
#
......
arch/ppc/kernel/traps.c
View file @ 92c06c66
......@@ -79,6 +79,7 @@ spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
void die(const char * str, struct pt_regs * fp, long err)
{
static int die_counter;
int nl = 0;
console_verbose();
spin_lock_irq(&die_lock);
#ifdef CONFIG_PMAC_BACKLIGHT
......@@ -86,6 +87,16 @@ void die(const char * str, struct pt_regs * fp, long err)
set_backlight_level(BACKLIGHT_MAX);
#endif
printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
#ifdef CONFIG_PREEMPT
printk("PREEMPT ");
nl = 1;
#endif
#ifdef CONFIG_SMP
printk("SMP NR_CPUS=%d ", NR_CPUS);
nl = 1;
#endif
if (nl)
printk("\n");
show_regs(fp);
spin_unlock_irq(&die_lock);
/* do_exit() should take care of panic'ing from an interrupt
......
arch/ppc/mm/cachemap.c
View file @ 92c06c66
......@@ -35,7 +35,7 @@
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/highmem.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <asm/pgalloc.h>
#include <asm/prom.h>
......@@ -143,15 +143,15 @@ void consistent_sync(void *vaddr, size_t size, int direction)
unsigned long end = start + size;
switch (direction) {
case PCI_DMA_NONE:
case DMA_NONE:
BUG();
case PCI_DMA_FROMDEVICE: /* invalidate only */
case DMA_FROMDEVICE: /* invalidate only */
invalidate_dcache_range(start, end);
break;
case PCI_DMA_TODEVICE: /* writeback only */
case DMA_TODEVICE: /* writeback only */
clean_dcache_range(start, end);
break;
case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */
case DMA_BIDIRECTIONAL: /* writeback and invalidate */
flush_dcache_range(start, end);
break;
}
......
arch/ppc/platforms/Makefile
View file @ 92c06c66
......@@ -41,11 +41,11 @@ obj-$(CONFIG_MVME5100) += mvme5100_setup.o mvme5100_pci.o
obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore_setup.o pcore_pci.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus_pci.o pplus_setup.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce_setup.o spruce_pci.o
obj-$(CONFIG_SPRUCE) += spruce.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
......
arch/ppc/platforms/pplus_pci.c → arch/ppc/platforms/pplus.c
View file @ 92c06c66
/*
* arch/ppc/platforms/pplus_pci.c
* arch/ppc/platforms/pplus.c
*
* PCI setup for MCG PowerPlus
* Board and PCI setup routines for MCG PowerPlus
*
* Author: Randy Vinson <rvinson@mvista.com>
*
......@@ -9,30 +9,51 @@
* Cort Dougan, Johnnie Peters, Matt Porter, and
* Troy Benjegerdes.
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/sections.h>
#include <asm/byteorder.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/pci-bridge.h>
#include <asm/residual.h>
#include <asm/irq.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/prep_nvram.h>
#include <asm/vga.h>
#include <asm/i8259.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/kgdb.h>
#include <asm/reg.h>
#include "pplus.h"
#undef DUMP_DBATS
TODC_ALLOC();
extern char saved_command_line[];
extern void pplus_setup_hose(void);
extern void pplus_set_VIA_IDE_native(void);
extern unsigned long loops_per_jiffy;
unsigned char *Motherboard_map_name;
/* Tables for known hardware */
......@@ -49,15 +70,15 @@ mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 19, 19, 19, 19 }, /* IDSEL 16 - PMC Slot 1 */
{ 0, 0, 0, 0 }, /* IDSEL 17 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 18 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 19 - unused */
{ 24, 25, 26, 27 }, /* IDSEL 20 - P2P bridge (to cPCI 1) */
{ 0, 0, 0, 0 }, /* IDSEL 21 - unused */
{ 28, 29, 30, 31 } /* IDSEL 22 - P2P bridge (to cPCI 2) */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{19, 19, 19, 19}, /* IDSEL 16 - PMC Slot 1 */
{ 0, 0, 0, 0}, /* IDSEL 17 - unused */
{ 0, 0, 0, 0}, /* IDSEL 18 - unused */
{ 0, 0, 0, 0}, /* IDSEL 19 - unused */
{24, 25, 26, 27}, /* IDSEL 20 - P2P bridge (to cPCI 1) */
{ 0, 0, 0, 0}, /* IDSEL 21 - unused */
{28, 29, 30, 31} /* IDSEL 22 - P2P bridge (to cPCI 2) */
};
const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
......@@ -76,13 +97,13 @@ sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
{ 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
{ 0, 0, 0, 0 }, /* IDSEL 18 - unused */
{ 0, 0, 0, 0 }, /* IDSEL 19 - unused */
{ 20, 0, 0, 0 } /* IDSEL 20 - P2P bridge (to cPCI) */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 0 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
{28, 25, 26, 27}, /* IDSEL 17 - PMC Slot 2 */
{ 0, 0, 0, 0}, /* IDSEL 18 - unused */
{ 0, 0, 0, 0}, /* IDSEL 19 - unused */
{20, 0, 0, 0} /* IDSEL 20 - P2P bridge (to cPCI) */
};
const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
......@@ -101,13 +122,13 @@ MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
{ 26, 27, 28, 25 }, /* IDSEL 17 - PMC Slot 2 */
{ 27, 28, 25, 26 } /* IDSEL 18 - PCI Slot 3 */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - unused */
{18, 0, 0, 0}, /* IDSEL 14 - Enet */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PMC Slot 1 */
{26, 27, 28, 25}, /* IDSEL 17 - PMC Slot 2 */
{27, 28, 25, 26} /* IDSEL 18 - PCI Slot 3 */
};
const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
......@@ -127,15 +148,15 @@ MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - unused */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PCI Slot 1P */
{ 26, 27, 28, 25 }, /* IDSEL 17 - PCI Slot 2P */
{ 27, 28, 25, 26 }, /* IDSEL 18 - PCI Slot 3P */
{ 26, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
{ 0, 0, 0, 0 } /* IDSEL 20 - P2P Bridge */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - unused */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PCI Slot 1P */
{26, 27, 28, 25}, /* IDSEL 17 - PCI Slot 2P */
{27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
{26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
{ 0, 0, 0, 0} /* IDSEL 20 - P2P Bridge */
};
const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
......@@ -186,15 +207,15 @@ Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
* A B C D
*/
{
{ 19, 0, 0, 0 }, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0 }, /* IDSEL 13 - Universe PCI - VME */
{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
{ 25, 26, 27, 28 }, /* IDSEL 16 - PCI/PMC Slot 1P */
{ 28, 25, 26, 27 }, /* IDSEL 17 - PCI/PMC Slot 2P */
{ 27, 28, 25, 26 }, /* IDSEL 18 - PCI Slot 3P */
{ 26, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
{ 25, 26, 27, 28 } /* IDSEL 20 - P2P Bridge */
{19, 0, 0, 0}, /* IDSEL 12 - SCSI */
{ 0, 0, 0, 0}, /* IDSEL 13 - Universe PCI - VME */
{18, 0, 0, 0}, /* IDSEL 14 - Enet 1 */
{ 0, 0, 0, 0}, /* IDSEL 15 - unused */
{25, 26, 27, 28}, /* IDSEL 16 - PCI/PMC Slot 1P */
{28, 25, 26, 27}, /* IDSEL 17 - PCI/PMC Slot 2P */
{27, 28, 25, 26}, /* IDSEL 18 - PCI Slot 3P */
{26, 0, 0, 0}, /* IDSEL 19 - Enet 2 */
{25, 26, 27, 28} /* IDSEL 20 - P2P Bridge */
};
const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
......@@ -208,65 +229,38 @@ Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
#define MOT_PROC2_BIT 0x800
static u_char pplus_openpic_initsenses[] __initdata = {
1, /* MVME2600_INT_SIO */
0, /* MVME2600_INT_FALCN_ECC_ERR */
1, /* MVME2600_INT_PCI_ETHERNET */
1, /* MVME2600_INT_PCI_SCSI */
1, /* MVME2600_INT_PCI_GRAPHICS */
1, /* MVME2600_INT_PCI_VME0 */
1, /* MVME2600_INT_PCI_VME1 */
1, /* MVME2600_INT_PCI_VME2 */
1, /* MVME2600_INT_PCI_VME3 */
1, /* MVME2600_INT_PCI_INTA */
1, /* MVME2600_INT_PCI_INTB */
1, /* MVME2600_INT_PCI_INTC */
1, /* MVME2600_INT_PCI_INTD */
1, /* MVME2600_INT_LM_SIG0 */
1, /* MVME2600_INT_LM_SIG1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
};
int mot_entry = -1;
int prep_keybd_present = 1;
int mot_multi = 0;
int __init raven_init(void)
{
unsigned short devid;
unsigned char base_mod;
/* set the MPIC base address */
early_write_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, 0x3cfc0000);
pplus_mpic_init(PREP_ISA_MEM_BASE);
OpenPIC_InitSenses = pplus_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
ppc_md.get_irq = openpic_get_irq;
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) ||
(base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
return 1;
}
struct brd_info {
int cpu_type; /* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
/* 0x100 mask assumes for Raven and Hawk boards that the level/edge
* are set */
int cpu_type;
/* 0x200 if this board has a Hawk chip. */
int base_type;
int max_cpu; /* ored with 0x80 if this board should be checked for multi CPU */
/* or'ed with 0x80 if this board should be checked for multi CPU */
int max_cpu;
const char *name;
int (*map_irq)(struct pci_dev *,
unsigned char,
unsigned char);
int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
};
struct brd_info mot_info[] = {
{0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
......@@ -303,14 +297,14 @@ void __init pplus_set_board_type(void)
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
/* Check for Hawk chip */
if (mot_info[entry].cpu_type & 0x200) {
if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
continue;
} else {
/* store the system config register for later use. */
ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
ProcInfo =
(unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
/* Check non hawk boards */
if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
......@@ -331,33 +325,32 @@ void __init pplus_set_board_type(void)
}
/* processor 1 not present and max processor zero indicated */
if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
if ((*ProcInfo & MOT_PROC2_BIT)
&& !(mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* processor 1 present and max processor zero indicated */
if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
if (!(*ProcInfo & MOT_PROC2_BIT)
&& (mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* Indicate to system if this is a multiprocessor board */
if (!(*ProcInfo & MOT_PROC2_BIT)) {
if (!(*ProcInfo & MOT_PROC2_BIT))
mot_multi = 1;
}
}
if (mot_entry == -1)
/* No particular cpu type found - assume Mesquite (MCP750) */
mot_entry = 1;
Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
}
void __init
pplus_pib_init(void)
void __init pplus_pib_init(void)
{
unsigned char reg;
unsigned short short_reg;
......@@ -379,15 +372,15 @@ pplus_pib_init(void)
reg |= 0x03; /* IDE: Chip Enable Bits */
pci_write_config_byte(dev, 0x40, reg);
}
if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_82C586_2,
dev)) && (dev->devfn = 0x5a)) {
/* Force correct USB interrupt */
dev->irq = 11;
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
dev->irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553, dev))) {
/* Clear PCI Interrupt Routing Control Register. */
......@@ -399,7 +392,7 @@ pplus_pib_init(void)
}
if ((dev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105, dev))){
PCI_DEVICE_ID_WINBOND_82C105, dev))) {
/*
* Disable LEGIRQ mode so PCI INTS are routed
* directly to the 8259 and enable both channels
......@@ -408,14 +401,11 @@ pplus_pib_init(void)
/* Force correct IDE interrupt */
dev->irq = 14;
pci_write_config_byte(dev,
PCI_INTERRUPT_LINE,
dev->irq);
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
}
void __init
pplus_set_VIA_IDE_legacy(void)
void __init pplus_set_VIA_IDE_legacy(void)
{
unsigned short vend, dev;
......@@ -424,7 +414,6 @@ pplus_set_VIA_IDE_legacy(void)
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put back original "standard" port base addresses */
......@@ -448,8 +437,7 @@ pplus_set_VIA_IDE_legacy(void)
}
}
void
pplus_set_VIA_IDE_native(void)
void pplus_set_VIA_IDE_native(void)
{
unsigned short vend, dev;
......@@ -458,7 +446,6 @@ pplus_set_VIA_IDE_native(void)
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put into native mode */
......@@ -470,33 +457,40 @@ pplus_set_VIA_IDE_native(void)
}
}
void __init
pplus_pcibios_fixup(void)
void __init pplus_pcibios_fixup(void)
{
printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
unsigned char reg;
unsigned short devid;
unsigned char base_mod;
printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
Motherboard_map_name);
/* Setup the Winbond or Via PIB */
pplus_pib_init();
}
static void __init
pplus_init_resource(struct resource *res, unsigned long start,
unsigned long end, int flags)
{
res->flags = flags;
res->start = start;
res->end = end;
res->name = "PCI host bridge";
res->parent = NULL;
res->sibling = NULL;
res->child = NULL;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
}
void __init
pplus_setup_hose(void)
void __init pplus_find_bridges(void)
{
struct pci_controller* hose;
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
......@@ -508,17 +502,25 @@ pplus_setup_hose(void)
hose->pci_mem_offset = PREP_ISA_MEM_BASE;
hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
pplus_init_resource(&hose->io_resource, 0x00000000, 0x0fffffff,
IORESOURCE_IO);
pplus_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfdffffff,
IORESOURCE_MEM);
pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = PPLUS_PCI_IO_START;
hose->io_space.end = PPLUS_PCI_IO_END;
hose->mem_space.start = PPLUS_PCI_MEM_START;
hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
hose->io_space.start = 0x00000000;
hose->io_space.end = 0x0fffffff;
hose->mem_space.start = 0x00000000;
hose->mem_space.end = 0x3cfbffff; /* MPIC at 0x3cfc0000-0x3dffffff */
if (pplus_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
!= 0) {
printk(KERN_CRIT "Could not initialize host bridge\n");
setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
}
pplus_set_VIA_IDE_legacy();
......@@ -526,5 +528,391 @@ pplus_setup_hose(void)
ppc_md.pcibios_fixup = pplus_pcibios_fixup;
ppc_md.pci_swizzle = common_swizzle;
}
static int pplus_show_cpuinfo(struct seq_file *m)
{
seq_printf(m, "vendor\t\t: Motorola MCG\n");
seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
return 0;
}
static void __init pplus_setup_arch(void)
{
struct pci_controller *hose;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: enter", 0);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: find_bridges", 0);
/* Setup PCI host bridge */
pplus_find_bridges();
hose = pci_bus_to_hose(0);
isa_io_base = (ulong) hose->io_base_virt;
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: set_board_type", 0);
pplus_set_board_type();
/* Enable L2. Assume we don't need to flush -- Cort */
*(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
printk(KERN_INFO "Motorola PowerPlus Platform\n");
printk(KERN_INFO
"Port by MontaVista Software, Inc. (source@mvista.com)\n");
#ifdef CONFIG_VGA_CONSOLE
/* remap the VGA memory */
vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
0x08000000);
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if (cmd_line[0] == '\0') {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
if (ppc_md.progress)
ppc_md.progress("pplus_setup_arch: exit", 0);
}
static void pplus_restart(char *cmd)
{
unsigned long i = 10000;
local_irq_disable();
/* set VIA IDE controller into native mode */
pplus_set_VIA_IDE_native();
/* set exception prefix high - to the prom */
_nmask_and_or_msr(0, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb(inb(0x92) & ~1L, 0x92);
/* signal a reset to system control port A - soft reset */
outb(inb(0x92) | 1, 0x92);
while (i != 0)
i++;
panic("restart failed\n");
}
static void pplus_halt(void)
{
/* set exception prefix high - to the prom */
_nmask_and_or_msr(MSR_EE, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb(inb(0x92) & ~1L, 0x92);
/* signal a reset to system control port A - soft reset */
outb(inb(0x92) | 1, 0x92);
while (1) ;
/*
* Not reached
*/
}
static void pplus_power_off(void)
{
pplus_halt();
}
static unsigned int pplus_irq_canonicalize(u_int irq)
{
if (irq == 2)
return 9;
else
return irq;
}
static void __init pplus_init_IRQ(void)
{
int i;
if (ppc_md.progress)
ppc_md.progress("init_irq: enter", 0);
OpenPIC_InitSenses = pplus_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
if (OpenPIC_Addr != NULL) {
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
openpic_init(NUM_8259_INTERRUPTS);
ppc_md.get_irq = openpic_get_irq;
}
for (i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
i8259_init(0);
if (ppc_md.progress)
ppc_md.progress("init_irq: exit", 0);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE stuff.
*/
static int pplus_ide_default_irq(unsigned long base)
{
switch (base) {
case 0x1f0:
return 14;
case 0x170:
return 15;
default:
return 0;
}
}
static unsigned long pplus_ide_default_io_base(int index)
{
switch (index) {
case 0:
return 0x1f0;
case 1:
return 0x170;
default:
return 0;
}
}
static void __init
pplus_ide_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port)
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
else
hw->io_ports[IDE_CONTROL_OFFSET] =
hw->io_ports[IDE_DATA_OFFSET] + 0x206;
if (irq != NULL)
*irq = pplus_ide_default_irq(data_port);
}
#endif
#ifdef CONFIG_SMP
/* PowerPlus (MTX) support */
static int __init smp_pplus_probe(void)
{
extern int mot_multi;
if (mot_multi) {
openpic_request_IPIs();
smp_hw_index[1] = 1;
return 2;
}
return 1;
}
static void __init smp_pplus_kick_cpu(int nr)
{
*(unsigned long *)KERNELBASE = nr;
asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
printk(KERN_INFO "CPU1 reset, waiting\n");
}
static void __init smp_pplus_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static struct smp_ops_t pplus_smp_ops = {
smp_openpic_message_pass,
smp_pplus_probe,
smp_pplus_kick_cpu,
smp_pplus_setup_cpu,
.give_timebase = smp_generic_give_timebase,
.take_timebase = smp_generic_take_timebase,
};
#endif /* CONFIG_SMP */
#ifdef DUMP_DBATS
static void print_dbat(int idx, u32 bat)
{
char str[64];
sprintf(str, "DBAT%c%c = 0x%08x\n",
(char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
ppc_md.progress(str, 0);
}
#define DUMP_DBAT(x) \
do { \
u32 __temp = mfspr(x);\
print_dbat(x, __temp); \
} while (0)
static void dump_dbats(void)
{
if (ppc_md.progress) {
DUMP_DBAT(DBAT0U);
DUMP_DBAT(DBAT0L);
DUMP_DBAT(DBAT1U);
DUMP_DBAT(DBAT1L);
DUMP_DBAT(DBAT2U);
DUMP_DBAT(DBAT2L);
DUMP_DBAT(DBAT3U);
DUMP_DBAT(DBAT3L);
}
}
#endif
static unsigned long __init pplus_find_end_of_memory(void)
{
unsigned long total;
if (ppc_md.progress)
ppc_md.progress("pplus_find_end_of_memory", 0);
#ifdef DUMP_DBATS
dump_dbats();
#endif
total = pplus_get_mem_size(PPLUS_HAWK_SMC_BASE);
return (total);
}
static void __init pplus_map_io(void)
{
io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
_PAGE_IO);
io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
}
static void __init pplus_init2(void)
{
#ifdef CONFIG_NVRAM
request_region(PREP_NVRAM_AS0, 0x8, "nvram");
#endif
request_region(0x20, 0x20, "pic1");
request_region(0xa0, 0x20, "pic2");
request_region(0x00, 0x20, "dma1");
request_region(0x40, 0x20, "timer");
request_region(0x80, 0x10, "dma page reg");
request_region(0xc0, 0x20, "dma2");
}
/*
* Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
* to 0xf0000000 to access Falcon/Raven or Hawk registers
*/
static __inline__ void pplus_set_bat(void)
{
/* wait for all outstanding memory accesses to complete */
mb();
/* setup DBATs */
mtspr(DBAT2U, 0x80001ffe);
mtspr(DBAT2L, 0x8000002a);
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
/* wait for updates */
mb();
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
pplus_set_bat();
isa_io_base = PREP_ISA_IO_BASE;
isa_mem_base = PREP_ISA_MEM_BASE;
pci_dram_offset = PREP_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = pplus_setup_arch;
ppc_md.show_cpuinfo = pplus_show_cpuinfo;
ppc_md.irq_canonicalize = pplus_irq_canonicalize;
ppc_md.init_IRQ = pplus_init_IRQ;
/* this gets changed later on if we have an OpenPIC -- Cort */
ppc_md.get_irq = i8259_irq;
ppc_md.init = pplus_init2;
ppc_md.restart = pplus_restart;
ppc_md.power_off = pplus_power_off;
ppc_md.halt = pplus_halt;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.find_end_of_memory = pplus_find_end_of_memory;
ppc_md.setup_io_mappings = pplus_map_io;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = pplus_ide_default_irq;
ppc_ide_md.default_io_base = pplus_ide_default_io_base;
ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
#ifdef CONFIG_SMP
ppc_md.smp_ops = &pplus_smp_ops;
#endif /* CONFIG_SMP */
}
arch/ppc/platforms/pplus.h 0 → 100644
View file @ 92c06c66
/*
* arch/ppc/platforms/pplus.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greerinclude/asm-ppc/hawk.h
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PPC_PPLUS_H
#define __PPC_PPLUS_H
#include <asm/io.h>
/*
* Due to limiations imposed by legacy hardware (primaryily IDE controllers),
* the PPLUS boards operate using a PReP address map.
*
* From Processor (physical) -> PCI:
* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI -> Processor (physical):
* System Memory: 0x80000000 -> 0x00000000
*/
#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
/* PCI Memory space mapping info */
#define PPLUS_PCI_MEM_SIZE 0x30000000U
#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
#define PPLUS_PCI_MEM_START 0x00000000U
#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
/* PCI I/O space mapping info */
#define PPLUS_PCI_IO_SIZE 0x10000000U
#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
#define PPLUS_PCI_IO_START 0x00000000U
#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
/* System memory mapping info */
#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
/* Define base addresses for important sets of registers */
#define PPLUS_HAWK_SMC_BASE 0xfef80000U
#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
#define PPLUS_SYS_CONFIG_REG 0xfef80400U
#define PPLUS_L2_CONTROL_REG 0x8000081cU
#define PPLUS_VGA_MEM_BASE 0xf0000000U
extern int pplus_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long pplus_get_mem_size(unsigned int smc_base);
extern int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __PPC_PPLUS_H */
arch/ppc/platforms/pplus_setup.c deleted 100644 → 0
View file @ 2c4dcfb7
/*
* arch/ppc/platforms/pplus_setup.c
*
* Board setup routines for MCG PowerPlus
*
* Author: Randy Vinson <rvinson@mvista.com>
*
* Derived from original PowerPlus PReP work by
* Cort Dougan, Johnnie Peters, Matt Porter, and
* Troy Benjegerdes.
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
#include <linux/reboot.h>
#include <linux/init.h>
#include <linux/initrd.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/timex.h>
#include <linux/pci.h>
#include <linux/irq.h>
#include <linux/ide.h>
#include <linux/kdev_t.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <asm/sections.h>
#include <asm/mmu.h>
#include <asm/system.h>
#include <asm/residual.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/cache.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mk48t59.h>
#include <asm/prep_nvram.h>
#include <asm/raven.h>
#include <asm/vga.h>
#include <asm/time.h>
#include <asm/i8259.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#undef DUMP_DBATS
TODC_ALLOC();
extern char saved_command_line[];
extern void pplus_setup_hose(void);
extern void pplus_set_VIA_IDE_native(void);
extern unsigned long loops_per_jiffy;
static int
pplus_show_cpuinfo(struct seq_file *m)
{
extern char *Motherboard_map_name;
seq_printf(m, "vendor\t\t: Motorola MCG\n");
seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
return 0;
}
static void __init
pplus_setup_arch(void)
{
unsigned char reg;
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: enter\n", 0);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000;
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: find_bridges\n", 0);
/* Setup PCI host bridge */
pplus_setup_hose();
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
/* Enable L2. Assume we don't need to flush -- Cort*/
*(unsigned char *)(0x8000081c) |= 3;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
printk(KERN_INFO "Motorola PowerPlus Platform\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: raven_init\n", 0);
raven_init();
#ifdef CONFIG_VGA_CONSOLE
/* remap the VGA memory */
vgacon_remap_base = 0xf0000000;
conswitchp = &vga_con;
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if ( cmd_line[0] == '\0' ) {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
if ( ppc_md.progress )
ppc_md.progress("pplus_setup_arch: exit\n", 0);
}
static void
pplus_restart(char *cmd)
{
unsigned long i = 10000;
local_irq_disable();
/* set VIA IDE controller into native mode */
pplus_set_VIA_IDE_native();
/* set exception prefix high - to the prom */
_nmask_and_or_msr(0, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb( inb(0x92) & ~1L , 0x92 );
/* signal a reset to system control port A - soft reset */
outb( inb(0x92) | 1 , 0x92 );
while ( i != 0 ) i++;
panic("restart failed\n");
}
static void
pplus_halt(void)
{
/* set exception prefix high - to the prom */
_nmask_and_or_msr(MSR_EE, MSR_IP);
/* make sure bit 0 (reset) is a 0 */
outb( inb(0x92) & ~1L , 0x92 );
/* signal a reset to system control port A - soft reset */
outb( inb(0x92) | 1 , 0x92 );
while ( 1 ) ;
/*
* Not reached
*/
}
static void
pplus_power_off(void)
{
pplus_halt();
}
static unsigned int
pplus_irq_canonicalize(u_int irq)
{
if (irq == 2)
{
return 9;
}
else
{
return irq;
}
}
static void __init
pplus_init_IRQ(void)
{
int i;
if (OpenPIC_Addr != NULL)
openpic_init(1, NUM_8259_INTERRUPTS, 0, -1);
for ( i = 0 ; i < NUM_8259_INTERRUPTS ; i++ )
irq_desc[i].handler = &i8259_pic;
i8259_init(NULL);
}
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
/*
* IDE stuff.
*/
static int
pplus_ide_default_irq(unsigned long base)
{
switch (base) {
case 0x1f0: return 14;
case 0x170: return 15;
default: return 0;
}
}
static unsigned long
pplus_ide_default_io_base(int index)
{
switch (index) {
case 0: return 0x1f0;
case 1: return 0x170;
default:
return 0;
}
}
static void __init
pplus_ide_init_hwif_ports (hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
int i;
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
hw->io_ports[i] = reg;
reg += 1;
}
if (ctrl_port) {
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
} else {
hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206;
}
if (irq != NULL)
*irq = pplus_ide_default_irq(data_port);
}
#endif
#ifdef CONFIG_SMP
/* PowerPlus (MTX) support */
static int __init
smp_pplus_probe(void)
{
extern int mot_multi;
if (mot_multi) {
openpic_request_IPIs();
smp_hw_index[1] = 1;
return 2;
}
return 1;
}
static void __init
smp_pplus_kick_cpu(int nr)
{
*(unsigned long *)KERNELBASE = nr;
asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
printk("CPU1 reset, waiting\n");
}
static void __init
smp_pplus_setup_cpu(int cpu_nr)
{
if (OpenPIC_Addr)
do_openpic_setup_cpu();
}
static struct smp_ops_t pplus_smp_ops = {
smp_openpic_message_pass,
smp_pplus_probe,
smp_pplus_kick_cpu,
smp_pplus_setup_cpu,
.give_timebase = smp_generic_give_timebase,
.take_timebase = smp_generic_take_timebase,
};
#endif /* CONFIG_SMP */
#ifdef DUMP_DBATS
static void print_dbat(int idx, u32 bat) {
char str[64];
sprintf(str, "DBAT%c%c = 0x%08x\n",
(char)((idx - DBAT0U) / 2) + '0',
(idx & 1) ? 'L' : 'U', bat);
ppc_md.progress(str, 0);
}
#define DUMP_DBAT(x) \
do { \
u32 __temp = mfspr(x);\
print_dbat(x, __temp); \
} while (0)
static void dump_dbats(void) {
if (ppc_md.progress) {
DUMP_DBAT(DBAT0U);
DUMP_DBAT(DBAT0L);
DUMP_DBAT(DBAT1U);
DUMP_DBAT(DBAT1L);
DUMP_DBAT(DBAT2U);
DUMP_DBAT(DBAT2L);
DUMP_DBAT(DBAT3U);
DUMP_DBAT(DBAT3L);
}
}
#endif
static unsigned long __init
pplus_find_end_of_memory(void)
{
unsigned long total;
if (ppc_md.progress)
ppc_md.progress("pplus_find_end_of_memory\n",0);
#ifdef DUMP_DBATS
dump_dbats();
#endif
total = pplus_get_mem_size(0xfef80000);
return (total);
}
static void __init
pplus_map_io(void)
{
io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
}
static void __init
pplus_init2(void)
{
#ifdef CONFIG_NVRAM
request_region(PREP_NVRAM_AS0, 0x8, "nvram");
#endif
request_region(0x20,0x20,"pic1");
request_region(0xa0,0x20,"pic2");
request_region(0x00,0x20,"dma1");
request_region(0x40,0x20,"timer");
request_region(0x80,0x10,"dma page reg");
request_region(0xc0,0x20,"dma2");
}
/*
* Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
* to 0xf0000000 to access Falcon/Raven or Hawk registers
*/
static __inline__ void
pplus_set_bat(void)
{
static int mapping_set = 0;
if (!mapping_set) {
/* wait for all outstanding memory accesses to complete */
mb();
/* setup DBATs */
mtspr(DBAT2U, 0x80001ffe);
mtspr(DBAT2L, 0x8000002a);
mtspr(DBAT3U, 0xf0001ffe);
mtspr(DBAT3L, 0xf000002a);
/* wait for updates */
mb();
mapping_set = 1;
}
return;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serial.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
void
pplus_progress(char *s, unsigned short hex)
{
volatile char c;
volatile unsigned long com_port;
u16 shift;
com_port = rs_table[0].port + isa_io_base;
shift = rs_table[0].iomem_reg_shift;
while ((c = *s++) != 0) {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = c;
if (c == '\n') {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = '\r';
}
}
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
pplus_set_bat();
isa_io_base = PREP_ISA_IO_BASE;
isa_mem_base = PREP_ISA_MEM_BASE;
pci_dram_offset = PREP_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_md.setup_arch = pplus_setup_arch;
ppc_md.show_percpuinfo = NULL;
ppc_md.show_cpuinfo = pplus_show_cpuinfo;
ppc_md.irq_canonicalize = pplus_irq_canonicalize;
ppc_md.init_IRQ = pplus_init_IRQ;
/* this gets changed later on if we have an OpenPIC -- Cort */
ppc_md.get_irq = i8259_irq;
ppc_md.init = pplus_init2;
ppc_md.restart = pplus_restart;
ppc_md.power_off = pplus_power_off;
ppc_md.halt = pplus_halt;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.find_end_of_memory = pplus_find_end_of_memory;
ppc_md.setup_io_mappings = pplus_map_io;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = pplus_progress;
#endif
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = pplus_ide_default_irq;
ppc_ide_md.default_io_base = pplus_ide_default_io_base;
ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SMP
ppc_md.smp_ops = &pplus_smp_ops;
#endif /* CONFIG_SMP */
}
arch/ppc/platforms/prep_setup.c
View file @ 92c06c66
......@@ -49,6 +49,7 @@
#include <asm/cache.h>
#include <asm/dma.h>
#include <asm/machdep.h>
#include <asm/mc146818rtc.h>
#include <asm/mk48t59.h>
#include <asm/prep_nvram.h>
#include <asm/raven.h>
......@@ -1023,8 +1024,10 @@ prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.time_init = todc_time_init;
if (_prep_type == _PREP_IBM) {
TODC_INIT(TODC_TYPE_MC146818, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.rtc_read_val = todc_mc146818_read_val;
ppc_md.rtc_write_val = todc_mc146818_write_val;
TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1),
8);
} else {
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
......
arch/ppc/platforms/spruce_setup.c → arch/ppc/platforms/spruce.c
View file @ 92c06c66
/*
* arch/ppc/platforms/spruce_setup.c
* arch/ppc/platforms/spruce.c
*
* Board setup routines for IBM Spruce
* Board and PCI setup routines for IBM Spruce
*
* Authors: Johnnie Peters <jpeters@mvista.com>
* Matt Porter <mporter@mvista.com>
* Author: MontaVista Software <source@mvista.com>
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* 2000-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -39,18 +38,73 @@
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <platforms/spruce.h>
#include <asm/todc.h>
#include <asm/bootinfo.h>
#include <asm/kgdb.h>
#include <syslib/cpc700.h>
extern void spruce_init_IRQ(void);
extern int spruce_get_irq(struct pt_regs *);
extern void spruce_setup_hose(void);
#include "spruce.h"
extern char cmd_line[];
static inline int
spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */
{24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */
{25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */
{26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
/*
* CPC700 PIC interrupt programming table
......@@ -122,7 +176,7 @@ spruce_early_serial_map(void)
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = uart_clk;
serial_req.irq = UART0_INT;
serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
serial_req.flags = ASYNC_BOOT_AUTOCONF;
serial_req.iotype = SERIAL_IO_MEM;
serial_req.membase = (u_char *)UART0_IO_BASE;
serial_req.regshift = 0;
......
arch/ppc/platforms/spruce.h
View file @ 92c06c66
......@@ -60,7 +60,7 @@
#define STD_UART_OP(num) \
{ 0, BASE_BAUD, 0, UART##num##_INT, \
ASYNC_BOOT_AUTOCONF, \
iomem_base: UART##num##_IO_BASE, \
iomem_base: (unsigned char *) UART##num##_IO_BASE, \
io_type: SERIAL_IO_MEM},
#define SERIAL_PORT_DFNS \
......
arch/ppc/platforms/spruce_pci.c deleted 100644 → 0
View file @ 2c4dcfb7
/*
* arch/ppc/platforms/spruce_pci.c
*
* PCI support for IBM Spruce
*
* Author: Johnnie Peters
* jpeters@mvista.com
*
* 2000 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <platforms/spruce.h>
#include <syslib/cpc700.h>
static inline int
spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{23, 24, 25, 26}, /* IDSEL 1 - PCI slot 3 */
{24, 25, 26, 23}, /* IDSEL 2 - PCI slot 2 */
{25, 26, 23, 24}, /* IDSEL 3 - PCI slot 1 */
{26, 23, 24, 25}, /* IDSEL 4 - PCI slot 0 */
};
const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
void __init
spruce_setup_hose(void)
{
struct pci_controller *hose;
/* Setup hose */
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_init_resource(&hose->io_resource,
SPRUCE_PCI_LOWER_IO,
SPRUCE_PCI_UPPER_IO,
IORESOURCE_IO,
"PCI host bridge");
pci_init_resource(&hose->mem_resources[0],
SPRUCE_PCI_LOWER_MEM,
SPRUCE_PCI_UPPER_MEM,
IORESOURCE_MEM,
"PCI host bridge");
hose->io_space.start = SPRUCE_PCI_LOWER_IO;
hose->io_space.end = SPRUCE_PCI_UPPER_IO;
hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
setup_indirect_pci(hose,
SPRUCE_PCI_CONFIG_ADDR,
SPRUCE_PCI_CONFIG_DATA);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = spruce_map_irq;
}
arch/ppc/platforms/spruce_serial.h deleted 100644 → 0
View file @ 2c4dcfb7
/*
* include/asm-ppc/spruce_serial.h
*
* Definitions for IBM Spruce reference board support
*
* Authors: Matt Porter and Johnnie Peters
* mporter@mvista.com
* jpeters@mvista.com
*
* 2000 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_SPRUCE_SERIAL_H
#define __ASMPPC_SPRUCE_SERIAL_H
#include <linux/config.h>
/* This is where the serial ports exist */
#define SPRUCE_SERIAL_1_ADDR 0xff600300
#define SPRUCE_SERIAL_2_ADDR 0xff600400
#define RS_TABLE_SIZE 4
/* Rate for the baud clock for the onboard serial chip */
#ifndef CONFIG_SPRUCE_BAUD_33M
#define BASE_BAUD (30000000 / 4 / 16)
#else
#define BASE_BAUD (33000000 / 4 / 16)
#endif
#ifndef SERIAL_MAGIC_KEY
#define kernel_debugger ppc_kernel_debug
#endif
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
#else
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
#endif
#define STD_SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, SPRUCE_SERIAL_1_ADDR, 3, STD_COM_FLAGS, /* ttyS0 */ \
iomem_base: (u8 *)SPRUCE_SERIAL_1_ADDR, \
io_type: SERIAL_IO_MEM }, \
{ 0, BASE_BAUD, SPRUCE_SERIAL_2_ADDR, 4, STD_COM_FLAGS, /* ttyS1 */ \
iomem_base: (u8 *)SPRUCE_SERIAL_2_ADDR, \
io_type: SERIAL_IO_MEM },
#define SERIAL_PORT_DFNS \
STD_SERIAL_PORT_DFNS
#endif /* __ASMPPC_SPRUCE_SERIAL_H */
arch/ppc/syslib/gen550_dbg.c
View file @ 92c06c66
......@@ -151,7 +151,7 @@ void
gen550_init(int i, struct uart_port *serial_req)
{
rs_table[i].io_type = serial_req->iotype;
rs_table[i].port = serial_req->line;
rs_table[i].port = serial_req->iobase;
rs_table[i].iomem_base = serial_req->membase;
rs_table[i].iomem_reg_shift = serial_req->regshift;
}
......
arch/ppc/syslib/indirect_pci.c
View file @ 92c06c66
......@@ -21,6 +21,12 @@
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#ifdef CONFIG_PPC_INDIRECT_PCI_BE
#define PCI_CFG_OUT out_be32
#else
#define PCI_CFG_OUT out_le32
#endif
static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
......@@ -37,9 +43,10 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
if (bus->number != hose->first_busno)
cfg_type = 1;
out_be32(hose->cfg_addr,
(((offset & 0xfc) | cfg_type) << 24) | (devfn << 16)
| ((bus->number - hose->bus_offset) << 8) | 0x80);
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | ((dev->bus->number - hose->bus_offset) << 16)
| (dev->devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
......@@ -75,9 +82,10 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
if (bus->number != hose->first_busno)
cfg_type = 1;
out_be32(hose->cfg_addr,
(((offset & 0xfc) | cfg_type) << 24) | (devfn << 16)
| ((bus->number - hose->bus_offset) << 8) | 0x80);
PCI_CFG_OUT(hose->cfg_addr,
(0x80000000 | ((dev->bus->number - hose->bus_offset) << 16)
| (dev->devfn << 8) | ((offset & 0xfc) | cfg_type)));
/*
* Note: the caller has already checked that offset is
* suitably aligned and that len is 1, 2 or 4.
......
arch/ppc/syslib/pplus_common.c
View file @ 92c06c66
......@@ -21,7 +21,7 @@
#include <asm/pci.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
/*
* The Falcon/Raven and HAWK has 4 sets of registers:
......@@ -95,10 +95,10 @@ pplus_init(struct pci_controller *hose,
/*
* Disable previous PPC->PCI mappings.
*/
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
/*
* Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
......@@ -113,21 +113,23 @@ pplus_init(struct pci_controller *hose,
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
/* Set up PPC->MPIC mapping on the bridge */
addr = processor_mpic_base |
(((processor_mpic_base + PPLUS_MPIC_SIZE) >> 16) - 1);
offset = 0xc2; /* No write posting for this PCI Mem space */
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), offset);
(((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
/* No write posting for this PCI Mem space */
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
(processor_pci_io_end - processor_pci_io_start + 1));
......@@ -137,8 +139,8 @@ pplus_init(struct pci_controller *hose,
* The PCI config addr/data pair based on start addr of PCI I/O space.
*/
setup_indirect_pci(hose,
processor_pci_io_start + PPLUS_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + PPLUS_PCI_CONFIG_DATA_OFF);
processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
/*
* Disable previous PCI->PPC mappings.
......@@ -161,10 +163,12 @@ pplus_init(struct pci_controller *hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_1,
processor_mpic_base | 0x0);
(processor_mpic_base -
processor_pci_mem_start +
hose->mem_space.start) | 0x0);
/* Map MPIC into vitual memory */
OpenPIC_Addr = ioremap(processor_mpic_base, PPLUS_MPIC_SIZE);
OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
return 0;
}
......@@ -181,14 +185,14 @@ pplus_init(struct pci_controller *hose,
#define MB (1024*1024)
static uint reg_offset_table[] __initdata = {
PPLUS_SMC_RAM_A_SIZE_REG_OFF,
PPLUS_SMC_RAM_B_SIZE_REG_OFF,
PPLUS_SMC_RAM_C_SIZE_REG_OFF,
PPLUS_SMC_RAM_D_SIZE_REG_OFF,
PPLUS_SMC_RAM_E_SIZE_REG_OFF,
PPLUS_SMC_RAM_F_SIZE_REG_OFF,
PPLUS_SMC_RAM_G_SIZE_REG_OFF,
PPLUS_SMC_RAM_H_SIZE_REG_OFF
HAWK_SMC_RAM_A_SIZE_REG_OFF,
HAWK_SMC_RAM_B_SIZE_REG_OFF,
HAWK_SMC_RAM_C_SIZE_REG_OFF,
HAWK_SMC_RAM_D_SIZE_REG_OFF,
HAWK_SMC_RAM_E_SIZE_REG_OFF,
HAWK_SMC_RAM_F_SIZE_REG_OFF,
HAWK_SMC_RAM_G_SIZE_REG_OFF,
HAWK_SMC_RAM_H_SIZE_REG_OFF
};
static uint falcon_size_table[] __initdata = {
......@@ -246,13 +250,13 @@ pplus_get_mem_size(uint smc_base)
size_table_entries = sizeof(falcon_size_table) /
sizeof(falcon_size_table[0]);
reg_limit = PPLUS_FALCON_SMC_REG_COUNT;
reg_limit = FALCON_SMC_REG_COUNT;
}
else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
size_table = hawk_size_table;
size_table_entries = sizeof(hawk_size_table) /
sizeof(hawk_size_table[0]);
reg_limit = PPLUS_HAWK_SMC_REG_COUNT;
reg_limit = HAWK_SMC_REG_COUNT;
}
else {
printk("pplus_get_mem_size: %s (0x%x)\n",
......
arch/ppc/syslib/todc_time.c
View file @ 92c06c66
......@@ -7,7 +7,7 @@
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -31,15 +31,13 @@
* 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
* 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
* set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
* address of the upper byte (leave NULL if using mv146818), and set
* address of the upper byte (leave NULL if using mc146818), and set
* 'nvram_data' to the address of the 8-bit data register.
*
* You also need to set 'ppc_md.nvram_read_val' and 'ppc_md.nvram_write_val' to
* the proper routines. There are standard ones defined further down in
* this file that you can use.
*
* There is a built in assumption that the RTC and NVRAM are accessed by the
* same mechanism (i.e., ppc_md.nvram_read_val, etc works for both).
* In order to break the assumption that the RTC and NVRAM are accessed by
* the same mechanism, you need to explicitly set 'ppc_md.rtc_read_val' and
* 'ppc_md.rtc_write_val', otherwise the values of 'ppc_md.rtc_read_val'
* and 'ppc_md.rtc_write_val' will be used.
*
* Note: Even though the documentation for the various RTC chips say that it
* take up to a second before it starts updating once the 'R' bit is
......@@ -50,6 +48,8 @@
* --MAG
*/
extern spinlock_t rtc_lock;
/*
* 'todc_info' should be initialized in your *_setup.c file to
* point to a fully initialized 'todc_info_t' structure.
......@@ -114,16 +114,63 @@ todc_m48txx_write_val(int addr, unsigned char val)
u_char
todc_mc146818_read_val(int addr)
{
outb(addr, todc_info->nvram_as0);
return inb(todc_info->nvram_data);
outb_p(addr, todc_info->nvram_as0);
return inb_p(todc_info->nvram_data);
}
void
todc_mc146818_write_val(int addr, unsigned char val)
{
outb(addr, todc_info->nvram_as0);
outb(val, todc_info->nvram_data);
return;
outb_p(addr, todc_info->nvram_as0);
outb_p(val, todc_info->nvram_data);
}
/*
* Routines to make RTC chips with NVRAM buried behind an addr/data pair
* have the NVRAM and clock regs appear at the same level.
* The NVRAM will appear to start at addr 0 and the clock regs will appear
* to start immediately after the NVRAM (actually, start at offset
* todc_info->nvram_size).
*/
static inline u_char
todc_read_val(int addr)
{
u_char val;
if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
if (addr < todc_info->nvram_size) { /* NVRAM */
ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
}
else { /* Clock Reg */
addr -= todc_info->nvram_size;
val = ppc_md.rtc_read_val(addr);
}
}
else {
val = ppc_md.rtc_read_val(addr);
}
return val;
}
static inline void
todc_write_val(int addr, u_char val)
{
if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
if (addr < todc_info->nvram_size) { /* NVRAM */
ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
}
else { /* Clock Reg */
addr -= todc_info->nvram_size;
ppc_md.rtc_write_val(addr, val);
}
}
else {
ppc_md.rtc_write_val(addr, val);
}
}
/*
......@@ -142,13 +189,14 @@ todc_mc146818_write_val(int addr, unsigned char val)
long __init
todc_time_init(void)
{
static u_char not_initialized = 1;
/* Make sure clocks are running */
if (not_initialized) {
u_char cntl_b;
cntl_b = ppc_md.nvram_read_val(todc_info->control_b);
if (!ppc_md.rtc_read_val)
ppc_md.rtc_read_val = ppc_md.nvram_read_val;
if (!ppc_md.rtc_write_val)
ppc_md.rtc_write_val = ppc_md.nvram_write_val;
cntl_b = todc_read_val(todc_info->control_b);
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
if ((cntl_b & 0x70) != 0x20) {
......@@ -159,34 +207,42 @@ todc_time_init(void)
cntl_b |= 0x20;
}
ppc_md.nvram_write_val(todc_info->control_b, cntl_b);
}
else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
todc_write_val(todc_info->control_b, cntl_b);
} else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
u_char mode;
mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
/* Make sure countdown clear is not set */
mode &= ~0x40;
/* Enable oscillator, extended register set */
mode |= 0x30;
todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
} else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
u_char month;
todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
month = ppc_md.nvram_read_val(todc_info->month);
month = todc_read_val(todc_info->month);
if ((month & 0x80) == 0x80) {
printk(KERN_INFO "TODC %s %s\n",
"real-time-clock was stopped.",
"Now starting...");
month &= ~0x80;
ppc_md.nvram_write_val(todc_info->month, month);
todc_write_val(todc_info->month, month);
}
cntl_b &= ~TODC_DS1501_CNTL_B_TE;
ppc_md.nvram_write_val(todc_info->control_b, cntl_b);
}
else { /* must be a m48txx type */
todc_write_val(todc_info->control_b, cntl_b);
} else { /* must be a m48txx type */
u_char cntl_a;
todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
cntl_a = ppc_md.nvram_read_val(todc_info->control_a);
cntl_a = todc_read_val(todc_info->control_a);
/* Check & clear STOP bit in control B register */
if (cntl_b & TODC_MK48TXX_DAY_CB) {
......@@ -197,22 +253,16 @@ todc_time_init(void)
cntl_a |= todc_info->enable_write;
cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
ppc_md.nvram_write_val(todc_info->control_a,
cntl_a);
ppc_md.nvram_write_val(todc_info->control_b,
cntl_b);
todc_write_val(todc_info->control_a, cntl_a);
todc_write_val(todc_info->control_b, cntl_b);
}
/* Make sure READ & WRITE bits are cleared. */
cntl_a &= ~(todc_info->enable_write |
todc_info->enable_read);
ppc_md.nvram_write_val(todc_info->control_a, cntl_a);
}
not_initialized = 0;
todc_write_val(todc_info->control_a, cntl_a);
}
return 0;
}
......@@ -231,7 +281,8 @@ todc_get_rtc_time(void)
uint limit, i;
u_char save_control, uip;
save_control = ppc_md.nvram_read_val(todc_info->control_a);
spin_lock(&rtc_lock);
save_control = todc_read_val(todc_info->control_a);
if (todc_info->rtc_type != TODC_TYPE_MC146818) {
limit = 1;
......@@ -241,9 +292,10 @@ todc_get_rtc_time(void)
case TODC_TYPE_DS1743:
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
case TODC_TYPE_DS1747:
case TODC_TYPE_DS17285:
break;
default:
ppc_md.nvram_write_val(todc_info->control_a,
todc_write_val(todc_info->control_a,
(save_control | todc_info->enable_read));
}
}
......@@ -253,19 +305,18 @@ todc_get_rtc_time(void)
for (i=0; i<limit; i++) {
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
uip = ppc_md.nvram_read_val(todc_info->RTC_FREQ_SELECT);
uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
}
sec = ppc_md.nvram_read_val(todc_info->seconds) & 0x7f;
min = ppc_md.nvram_read_val(todc_info->minutes) & 0x7f;
hour = ppc_md.nvram_read_val(todc_info->hours) & 0x3f;
day = ppc_md.nvram_read_val(todc_info->day_of_month) & 0x3f;
mon = ppc_md.nvram_read_val(todc_info->month) & 0x1f;
year = ppc_md.nvram_read_val(todc_info->year) & 0xff;
sec = todc_read_val(todc_info->seconds) & 0x7f;
min = todc_read_val(todc_info->minutes) & 0x7f;
hour = todc_read_val(todc_info->hours) & 0x3f;
day = todc_read_val(todc_info->day_of_month) & 0x3f;
mon = todc_read_val(todc_info->month) & 0x1f;
year = todc_read_val(todc_info->year) & 0xff;
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
uip |= ppc_md.nvram_read_val(
todc_info->RTC_FREQ_SELECT);
uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
if ((uip & RTC_UIP) == 0) break;
}
}
......@@ -276,13 +327,15 @@ todc_get_rtc_time(void)
case TODC_TYPE_DS1743:
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
case TODC_TYPE_DS1747:
case TODC_TYPE_DS17285:
break;
default:
save_control &= ~(todc_info->enable_read);
ppc_md.nvram_write_val(todc_info->control_a,
todc_write_val(todc_info->control_a,
save_control);
}
}
spin_unlock(&rtc_lock);
if ((todc_info->rtc_type != TODC_TYPE_MC146818) ||
((save_control & RTC_DM_BINARY) == 0) ||
......@@ -310,19 +363,19 @@ todc_set_rtc_time(unsigned long nowtime)
struct rtc_time tm;
u_char save_control, save_freq_select;
spin_lock(&rtc_lock);
to_tm(nowtime, &tm);
save_control = ppc_md.nvram_read_val(todc_info->control_a);
save_control = todc_read_val(todc_info->control_a);
/* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
ppc_md.nvram_write_val(todc_info->control_a,
todc_write_val(todc_info->control_a,
(save_control | todc_info->enable_write));
save_control &= ~(todc_info->enable_write); /* in case it was set */
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
save_freq_select =
ppc_md.nvram_read_val(todc_info->RTC_FREQ_SELECT);
ppc_md.nvram_write_val(todc_info->RTC_FREQ_SELECT,
save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
todc_write_val(todc_info->RTC_FREQ_SELECT,
save_freq_select | RTC_DIV_RESET2);
}
......@@ -341,19 +394,19 @@ todc_set_rtc_time(unsigned long nowtime)
BIN_TO_BCD(tm.tm_year);
}
ppc_md.nvram_write_val(todc_info->seconds, tm.tm_sec);
ppc_md.nvram_write_val(todc_info->minutes, tm.tm_min);
ppc_md.nvram_write_val(todc_info->hours, tm.tm_hour);
ppc_md.nvram_write_val(todc_info->month, tm.tm_mon);
ppc_md.nvram_write_val(todc_info->day_of_month, tm.tm_mday);
ppc_md.nvram_write_val(todc_info->year, tm.tm_year);
todc_write_val(todc_info->seconds, tm.tm_sec);
todc_write_val(todc_info->minutes, tm.tm_min);
todc_write_val(todc_info->hours, tm.tm_hour);
todc_write_val(todc_info->month, tm.tm_mon);
todc_write_val(todc_info->day_of_month, tm.tm_mday);
todc_write_val(todc_info->year, tm.tm_year);
ppc_md.nvram_write_val(todc_info->control_a, save_control);
todc_write_val(todc_info->control_a, save_control);
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
ppc_md.nvram_write_val(todc_info->RTC_FREQ_SELECT,
save_freq_select);
todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
}
spin_unlock(&rtc_lock);
return 0;
}
......@@ -367,30 +420,28 @@ static unsigned char __init todc_read_timereg(int addr)
switch (todc_info->rtc_type) {
case TODC_TYPE_DS1557:
case TODC_TYPE_DS1743:
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
case TODC_TYPE_DS1747:
case TODC_TYPE_DS17285:
case TODC_TYPE_MC146818:
break;
default:
save_control =
ppc_md.nvram_read_val(todc_info->control_a);
ppc_md.nvram_write_val(todc_info->control_a,
save_control = todc_read_val(todc_info->control_a);
todc_write_val(todc_info->control_a,
(save_control | todc_info->enable_read));
}
val = ppc_md.nvram_read_val(addr);
val = todc_read_val(addr);
switch (todc_info->rtc_type) {
case TODC_TYPE_DS1557:
case TODC_TYPE_DS1743:
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
case TODC_TYPE_DS1747:
case TODC_TYPE_DS17285:
case TODC_TYPE_MC146818:
break;
default:
save_control &= ~(todc_info->enable_read);
ppc_md.nvram_write_val(todc_info->control_a,
save_control);
todc_write_val(todc_info->control_a, save_control);
}
return val;
......@@ -412,7 +463,7 @@ todc_calibrate_decr(void)
/*
* Actually this is bad for precision, we should have a loop in
* which we only read the seconds counter. nvram_read_val writes
* which we only read the seconds counter. todc_read_val writes
* the address bytes on every call and this takes a lot of time.
* Perhaps an nvram_wait_change method returning a time
* stamp with a loop count as parameter would be the solution.
......
include/asm-ppc/dma-mapping.h
View file @ 92c06c66
#include <asm-generic/dma-mapping.h>
/*
* This is based on both include/asm-sh/dma-mapping.h and
* include/asm-ppc/pci.h
*/
#ifndef __ASM_PPC_DMA_MAPPING_H
#define __ASM_PPC_DMA_MAPPING_H
#include <linux/config.h>
/* we implement the API below in terms of the existing PCI one,
* so include it */
#include <linux/pci.h>
/* need struct page definitions */
#include <linux/mm.h>
#include <linux/device.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#define dma_supported(dev, mask) (1)
static inline int dma_set_mask(struct device *dev, u64 dma_mask)
{
if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = dma_mask;
return 0;
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, int flag)
{
#ifdef CONFIG_PCI
if (dev && dev->bus == &pci_bus_type)
return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
#endif
return consistent_alloc(flag, size, dma_handle);
}
static inline void
dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
#ifdef CONFIG_PCI
if (dev && dev->bus == &pci_bus_type) {
pci_free_consistent(to_pci_dev(dev), size, vaddr, dma_handle);
return;
}
#endif
consistent_free(vaddr);
}
static inline dma_addr_t
dma_map_single(struct device *dev, void *ptr, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync(ptr, size, direction);
return virt_to_bus(ptr);
}
/* We do nothing. */
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline dma_addr_t
dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync_page(page, offset, size, direction);
return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
}
/* We do nothing. */
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline int
dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++) {
BUG_ON(!sg->page);
consistent_sync_page(sg->page, sg->offset,
sg->length, direction);
sg->dma_address = page_to_bus(sg->page) + sg->offset;
}
return nents;
}
/* We don't do anything here. */
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
consistent_sync(bus_to_virt(dma_handle), size, direction);
}
static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nelems; i++, sg++)
consistent_sync_page(sg->page, sg->offset,
sg->length, direction);
}
/* Now for the API extensions over the pci_ one */
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_is_consistent(d) (1)
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline void
dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything, that's all the pci API can do */
dma_sync_single(dev, dma_handle, offset + size, direction);
}
static inline void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction direction)
{
consistent_sync(vaddr, size, (int)direction);
}
#endif /* __ASM_PPC_DMA_MAPPING_H */
include/asm-ppc/hawk.h 0 → 100644
View file @ 92c06c66
/*
* include/asm-ppc/hawk.h
*
* Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_H
#define __ASMPPC_HAWK_H
#include <asm/pci-bridge.h>
#include <asm/hawk_defs.h>
extern int hawk_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
include/asm-ppc/pplus.h → include/asm-ppc/hawk_defs.h
View file @ 92c06c66
/*
* include/asm-ppc/pplus.h
* include/asm-ppc/hawk_defs.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_PPLUS_H
#define __ASMPPC_PPLUS_H
#ifndef __ASMPPC_HAWK_DEFS_H
#define __ASMPPC_HAWK_DEFS_H
#include <asm/pci-bridge.h>
......@@ -27,66 +29,48 @@
* 4) System Memory Controller (SMC) registers.
*/
#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057
#define PPLUS_HAWK_VEND_DEV_ID 0x48031057
#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc
#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc
#define PPLUS_MPIC_SIZE 0x00040000U
#define PPLUS_SMC_SIZE 0x00001000U
#define HAWK_MPIC_SIZE 0x00040000U
#define HAWK_SMC_SIZE 0x00001000U
/*
* Define PPC register offsets.
*/
#define PPLUS_PPC_XSADD0_OFF 0x40
#define PPLUS_PPC_XSOFF0_OFF 0x44
#define PPLUS_PPC_XSADD1_OFF 0x48
#define PPLUS_PPC_XSOFF1_OFF 0x4c
#define PPLUS_PPC_XSADD2_OFF 0x50
#define PPLUS_PPC_XSOFF2_OFF 0x54
#define PPLUS_PPC_XSADD3_OFF 0x58
#define PPLUS_PPC_XSOFF3_OFF 0x5c
#define HAWK_PPC_XSADD0_OFF 0x40
#define HAWK_PPC_XSOFF0_OFF 0x44
#define HAWK_PPC_XSADD1_OFF 0x48
#define HAWK_PPC_XSOFF1_OFF 0x4c
#define HAWK_PPC_XSADD2_OFF 0x50
#define HAWK_PPC_XSOFF2_OFF 0x54
#define HAWK_PPC_XSADD3_OFF 0x58
#define HAWK_PPC_XSOFF3_OFF 0x5c
/*
* Define PCI register offsets.
*/
#define PPLUS_PCI_PSADD0_OFF 0x80
#define PPLUS_PCI_PSOFF0_OFF 0x84
#define PPLUS_PCI_PSADD1_OFF 0x88
#define PPLUS_PCI_PSOFF1_OFF 0x8c
#define PPLUS_PCI_PSADD2_OFF 0x90
#define PPLUS_PCI_PSOFF2_OFF 0x94
#define PPLUS_PCI_PSADD3_OFF 0x98
#define PPLUS_PCI_PSOFF3_OFF 0x9c
#define HAWK_PCI_PSADD0_OFF 0x80
#define HAWK_PCI_PSOFF0_OFF 0x84
#define HAWK_PCI_PSADD1_OFF 0x88
#define HAWK_PCI_PSOFF1_OFF 0x8c
#define HAWK_PCI_PSADD2_OFF 0x90
#define HAWK_PCI_PSOFF2_OFF 0x94
#define HAWK_PCI_PSADD3_OFF 0x98
#define HAWK_PCI_PSOFF3_OFF 0x9c
/*
* Define the System Memory Controller (SMC) register offsets.
*/
#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10
#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11
#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12
#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13
#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define PPLUS_FALCON_SMC_REG_COUNT 4
#define PPLUS_HAWK_SMC_REG_COUNT 8
int pplus_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base);
unsigned long pplus_get_mem_size(uint smc_base);
int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10
#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11
#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12
#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13
#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define FALCON_SMC_REG_COUNT 4
#define HAWK_SMC_REG_COUNT 8
#endif /* __ASMPPC_HAWK_DEFS_H */
include/asm-ppc/io.h
View file @ 92c06c66
......@@ -82,7 +82,6 @@ extern unsigned long pci_dram_offset;
#define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
#ifdef CONFIG_PPC_PMAC
/*
* On powermacs, we will get a machine check exception if we
* try to read data from a non-existent I/O port. Because the
......@@ -94,7 +93,7 @@ extern unsigned long pci_dram_offset;
* all PPC implementations tested so far. The twi and isync are
* needed on the 601 (in fact twi; sync works too), the isync and
* nop are needed on 604[e|r], and any of twi, sync or isync will
* work on 603[e], 750, 74x0.
* work on 603[e], 750, 74xx.
* The twi creates an explicit data dependency on the returned
* value which seems to be needed to make the 601 wait for the
* load to finish.
......@@ -140,27 +139,17 @@ extern __inline__ void name(unsigned int val, unsigned int port) \
}
__do_in_asm(inb, "lbzx")
__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
__do_in_asm(inw, "lhz%U1%X1")
__do_in_asm(inl, "lwz%U1%X1")
__do_out_asm(outl,"stw%U0%X0")
__do_out_asm(outw, "sth%U0%X0")
#else
__do_in_asm(inw, "lhbrx")
__do_in_asm(inl, "lwbrx")
__do_out_asm(outb, "stbx")
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")
#elif defined(CONFIG_APUS)
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#define inw(port) in_be16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_be32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
#else /* not APUS or PMAC */
#define inb(port) in_8((u8 *)((port)+_IO_BASE))
#define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
#define inw(port) in_le16((u16 *)((port)+_IO_BASE))
#define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
#define inl(port) in_le32((u32 *)((port)+_IO_BASE))
#define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
#endif
#define inb_p(port) inb((port))
......@@ -291,12 +280,19 @@ extern inline void eieio(void)
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(volatile unsigned char *addr)
{
int ret;
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__(
"lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -309,7 +305,9 @@ extern inline int in_le16(volatile unsigned short *addr)
{
int ret;
__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
__asm__ __volatile__("lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
......@@ -318,7 +316,9 @@ extern inline int in_be16(volatile unsigned short *addr)
{
int ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -337,7 +337,9 @@ extern inline unsigned in_le32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
......@@ -346,7 +348,9 @@ extern inline unsigned in_be32(volatile unsigned *addr)
{
unsigned ret;
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
__asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
......@@ -417,7 +421,7 @@ extern void consistent_sync_page(struct page *page, unsigned long offset,
#define dma_cache_wback_inv(_start,_size) do { } while (0)
#define consistent_alloc(gfp, size, handle) NULL
#define consistent_free(addr, size) do { } while (0)
#define consistent_free(addr) do { } while (0)
#define consistent_sync(addr, size, rw) do { } while (0)
#define consistent_sync_page(pg, off, sz, rw) do { } while (0)
......
include/asm-ppc/machdep.h
View file @ 92c06c66
......@@ -43,6 +43,8 @@ struct machdep_calls {
long (*time_init)(void); /* Optional, may be NULL */
int (*set_rtc_time)(unsigned long nowtime);
unsigned long (*get_rtc_time)(void);
unsigned char (*rtc_read_val)(int addr);
void (*rtc_write_val)(int addr, unsigned char val);
void (*calibrate_decr)(void);
void (*heartbeat)(void);
......
include/asm-ppc/serial.h
View file @ 92c06c66
......@@ -27,7 +27,7 @@
#elif defined(CONFIG_SANDPOINT)
#include <platforms/sandpoint.h>
#elif defined(CONFIG_SPRUCE)
#include <platforms/spruce_serial.h>
#include <platforms/spruce.h>
#elif defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#else
......
include/asm-ppc/todc.h
View file @ 92c06c66
......@@ -29,9 +29,9 @@ typedef struct {
* Following are the addresses of the AS0, AS1, and DATA registers
* of these chips. Note that these are board-specific.
*/
unsigned char *nvram_as0;
unsigned char *nvram_as1;
unsigned char *nvram_data;
unsigned int nvram_as0;
unsigned int nvram_as1;
unsigned int nvram_data;
/*
* Define bits to stop external set of regs from changing so
......@@ -46,6 +46,9 @@ typedef struct {
*/
int as0_bits;
int nvram_size; /* Size of NVRAM on chip */
int sw_flags; /* Software control flags */
/* Following are the register offsets for the particular chip */
int year;
int month;
......@@ -64,6 +67,14 @@ typedef struct {
int alarm_seconds;
int century;
int flags;
/*
* Some RTC chips have their NVRAM buried behind a addr/data pair of
* regs on the first level/clock registers. The following fields
* are the addresses for those addr/data regs.
*/
int nvram_addr_reg;
int nvram_data_reg;
} todc_info_t;
/*
......@@ -86,7 +97,8 @@ typedef struct {
#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
#define TODC_TYPE_MC146818 100 /* Leave room for more m48txx's */
#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
/*
* Bit to clear/set to enable reads/writes to the chip
......@@ -97,10 +109,19 @@ typedef struct {
#define TODC_DS1501_CNTL_B_TE 0x80
/*
* Define flag bits used by todc routines.
*/
#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
/*
* Define the values for the various RTC's that should to into the todc_info
* table.
* Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
* matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
*/
#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
#define TODC_TYPE_MK48T35_SW_FLAGS 0
#define TODC_TYPE_MK48T35_YEAR 0x7fff
#define TODC_TYPE_MK48T35_MONTH 0x7ffe
#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
......@@ -118,7 +139,11 @@ typedef struct {
#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
#define TODC_TYPE_MK48T35_CENTURY 0x0000
#define TODC_TYPE_MK48T35_FLAGS 0x0000
#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
#define TODC_TYPE_MK48T37_SW_FLAGS 0
#define TODC_TYPE_MK48T37_YEAR 0x7fff
#define TODC_TYPE_MK48T37_MONTH 0x7ffe
#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
......@@ -136,7 +161,11 @@ typedef struct {
#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
#define TODC_TYPE_MK48T59_SW_FLAGS 0
#define TODC_TYPE_MK48T59_YEAR 0x1fff
#define TODC_TYPE_MK48T59_MONTH 0x1ffe
#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
......@@ -154,25 +183,33 @@ typedef struct {
#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
#define TODC_TYPE_MK48T59_CENTURY 0x1fff
#define TODC_TYPE_MK48T59_FLAGS 0x1fff
#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1501_YEAR 0x06
#define TODC_TYPE_DS1501_MONTH 0x05
#define TODC_TYPE_DS1501_DOM 0x04 /* Day of Month */
#define TODC_TYPE_DS1501_DOW 0x03 /* Day of Week */
#define TODC_TYPE_DS1501_HOURS 0x02
#define TODC_TYPE_DS1501_MINUTES 0x01
#define TODC_TYPE_DS1501_SECONDS 0x00
#define TODC_TYPE_DS1501_CNTL_B 0x0f
#define TODC_TYPE_DS1501_CNTL_A 0x0f
#define TODC_TYPE_DS1501_WATCHDOG 0xff
#define TODC_TYPE_DS1501_INTERRUPTS 0xff
#define TODC_TYPE_DS1501_ALARM_DATE 0x0b
#define TODC_TYPE_DS1501_ALARM_HOUR 0x0a
#define TODC_TYPE_DS1501_ALARM_MINUTES 0x09
#define TODC_TYPE_DS1501_ALARM_SECONDS 0x08
#define TODC_TYPE_DS1501_CENTURY 0x07
#define TODC_TYPE_DS1501_FLAGS 0xff
#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
#define TODC_TYPE_DS1557_SW_FLAGS 0
#define TODC_TYPE_DS1557_YEAR 0x7ffff
#define TODC_TYPE_DS1557_MONTH 0x7fffe
#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
......@@ -190,7 +227,11 @@ typedef struct {
#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
#define TODC_TYPE_DS1557_CENTURY 0x7fff8
#define TODC_TYPE_DS1557_FLAGS 0x7fff0
#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
#define TODC_TYPE_DS1643_SW_FLAGS 0
#define TODC_TYPE_DS1643_YEAR 0x1fff
#define TODC_TYPE_DS1643_MONTH 0x1ffe
#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
......@@ -208,7 +249,11 @@ typedef struct {
#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
#define TODC_TYPE_DS1643_CENTURY 0x1ff8
#define TODC_TYPE_DS1643_FLAGS 0x1fff
#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
#define TODC_TYPE_DS1693_SW_FLAGS 0
#define TODC_TYPE_DS1693_YEAR 0x09
#define TODC_TYPE_DS1693_MONTH 0x08
#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
......@@ -226,7 +271,11 @@ typedef struct {
#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
#define TODC_TYPE_DS1693_CENTURY 0x48
#define TODC_TYPE_DS1693_FLAGS 0xff
#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
#define TODC_TYPE_DS1743_SW_FLAGS 0
#define TODC_TYPE_DS1743_YEAR 0x1fff
#define TODC_TYPE_DS1743_MONTH 0x1ffe
#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
......@@ -244,7 +293,11 @@ typedef struct {
#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
#define TODC_TYPE_DS1743_CENTURY 0x1ff8
#define TODC_TYPE_DS1743_FLAGS 0x1fff
#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
#define TODC_TYPE_DS1746_SW_FLAGS 0
#define TODC_TYPE_DS1746_YEAR 0x1ffff
#define TODC_TYPE_DS1746_MONTH 0x1fffe
#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
......@@ -262,16 +315,20 @@ typedef struct {
#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
#define TODC_TYPE_DS1746_CENTURY 0x00000
#define TODC_TYPE_DS1746_FLAGS 0x00000
#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
#define TODC_TYPE_DS1747_YEAR 0x1ffff
#define TODC_TYPE_DS1747_MONTH 0x1fffe
#define TODC_TYPE_DS1747_DOM 0x1fffd /* Day of Month */
#define TODC_TYPE_DS1747_DOW 0x1fffc /* Day of Week */
#define TODC_TYPE_DS1747_HOURS 0x1fffb
#define TODC_TYPE_DS1747_MINUTES 0x1fffa
#define TODC_TYPE_DS1747_SECONDS 0x1fff9
#define TODC_TYPE_DS1747_CNTL_B 0x1fff9
#define TODC_TYPE_DS1747_CNTL_A 0x1fff8 /* control_a R/W regs */
#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
#define TODC_TYPE_DS1747_SW_FLAGS 0
#define TODC_TYPE_DS1747_YEAR 0x7ffff
#define TODC_TYPE_DS1747_MONTH 0x7fffe
#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
#define TODC_TYPE_DS1747_HOURS 0x7fffb
#define TODC_TYPE_DS1747_MINUTES 0x7fffa
#define TODC_TYPE_DS1747_SECONDS 0x7fff9
#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
#define TODC_TYPE_DS1747_WATCHDOG 0x00000
#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
......@@ -280,7 +337,35 @@ typedef struct {
#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
#define TODC_TYPE_DS1747_CENTURY 0x00000
#define TODC_TYPE_DS1747_FLAGS 0x00000
#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
#define TODC_TYPE_DS17285_WATCHDOG 0
#define TODC_TYPE_DS17285_INTERRUPTS 0
#define TODC_TYPE_DS17285_ALARM_DATE 0
#define TODC_TYPE_DS17285_CENTURY 0
#define TODC_TYPE_DS17285_FLAGS 0
#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
#define TODC_TYPE_MC146818_SW_FLAGS 0
#define TODC_TYPE_MC146818_YEAR 0x09
#define TODC_TYPE_MC146818_MONTH 0x08
#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
......@@ -298,7 +383,11 @@ typedef struct {
#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
#define TODC_TYPE_MC146818_CENTURY 0xff
#define TODC_TYPE_MC146818_FLAGS 0xff
#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
#define TODC_TYPE_PC97307_SW_FLAGS 0
#define TODC_TYPE_PC97307_YEAR 0x09
#define TODC_TYPE_PC97307_MONTH 0x08
#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
......@@ -316,6 +405,8 @@ typedef struct {
#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
#define TODC_TYPE_PC97307_CENTURY 0xff
#define TODC_TYPE_PC97307_FLAGS 0xff
#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
/*
* Define macros to allocate and init the todc_info_t table that will
......@@ -328,12 +419,15 @@ typedef struct {
#define TODC_INIT(clock_type, as0, as1, data, bits) { \
todc_info->rtc_type = clock_type; \
\
todc_info->nvram_as0 = (unsigned char *)(as0); \
todc_info->nvram_as1 = (unsigned char *)(as1); \
todc_info->nvram_data = (unsigned char *)(data); \
todc_info->nvram_as0 = (unsigned int)(as0); \
todc_info->nvram_as1 = (unsigned int)(as1); \
todc_info->nvram_data = (unsigned int)(data); \
\
todc_info->as0_bits = (bits); \
\
todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
todc_info->sw_flags = clock_type ##_SW_FLAGS; \
\
todc_info->year = clock_type ##_YEAR; \
todc_info->month = clock_type ##_MONTH; \
todc_info->day_of_month = clock_type ##_DOM; \
......@@ -351,6 +445,9 @@ typedef struct {
todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
todc_info->century = clock_type ##_CENTURY; \
todc_info->flags = clock_type ##_FLAGS; \
\
todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
}
extern todc_info_t *todc_info;
......
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