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Commit 9346dba5 authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: standardize DMAC traffic control MMRs & MDMA MMRs 

Use the same naming convention for DMA traffic MMRs (most were legacy
anyways) so we can avoid useless ifdef trees.

Same goes for MDMA names -- this actually allows us to undo a bunch of
ifdef redirects that existed for this purpose alone.
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 6c8e75a0
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Showing with 698 additions and 973 deletions
arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
View file @ 9346dba5
...@@ -377,16 +377,10 @@ ...@@ -377,16 +377,10 @@
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
/* DMA Controller */ /* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
......
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View file @ 9346dba5
...@@ -215,12 +215,8 @@ ...@@ -215,12 +215,8 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
......
arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
View file @ 9346dba5
...@@ -394,16 +394,10 @@ ...@@ -394,16 +394,10 @@
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER, val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT, val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
/* DMA Controller */ /* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
......
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View file @ 9346dba5
...@@ -215,12 +215,8 @@ ...@@ -215,12 +215,8 @@
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
......
arch/blackfin/mach-bf533/include/mach/cdefBF532.h
View file @ 9346dba5
...@@ -66,16 +66,10 @@ ...@@ -66,16 +66,10 @@
#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
/* DMA Traffic controls */ /* DMA Traffic controls */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val) #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) #define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
......
arch/blackfin/mach-bf533/include/mach/defBF532.h
View file @ 9346dba5
...@@ -182,12 +182,8 @@ ...@@ -182,12 +182,8 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic controls */ /* DMA Traffic controls */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
......
arch/blackfin/mach-bf537/include/mach/cdefBF534.h
View file @ 9346dba5
...@@ -355,16 +355,10 @@ ...@@ -355,16 +355,10 @@
#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) #define bfin_read_DMAC_TC_PER() bfin_read16(DMAC_TC_PER)
#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val) #define bfin_write_DMAC_TC_PER(val) bfin_write16(DMAC_TC_PER,val)
#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) #define bfin_read_DMAC_TC_CNT() bfin_read16(DMAC_TC_CNT)
#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val) #define bfin_write_DMAC_TC_CNT(val) bfin_write16(DMAC_TC_CNT,val)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
/* DMA Controller */ /* DMA Controller */
#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
......
arch/blackfin/mach-bf537/include/mach/defBF534.h
View file @ 9346dba5
...@@ -193,12 +193,8 @@ ...@@ -193,12 +193,8 @@
#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
/* DMA Traffic Control Registers */ /* DMA Traffic Control Registers */
#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
......
arch/blackfin/mach-bf538/dma.c
View file @ 9346dba5
...@@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { ...@@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA17_NEXT_DESC_PTR, (struct dma_register *) DMA17_NEXT_DESC_PTR,
(struct dma_register *) DMA18_NEXT_DESC_PTR, (struct dma_register *) DMA18_NEXT_DESC_PTR,
(struct dma_register *) DMA19_NEXT_DESC_PTR, (struct dma_register *) DMA19_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D0_NEXT_DESC_PTR, (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S0_NEXT_DESC_PTR, (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA0_S1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
}; };
EXPORT_SYMBOL(dma_io_base_addr); EXPORT_SYMBOL(dma_io_base_addr);
......
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View file @ 9346dba5
...@@ -1615,14 +1615,14 @@ ...@@ -1615,14 +1615,14 @@
#define CTYPE 0x40 /* DMA Channel Type */ #define CTYPE 0x40 /* DMA Channel Type */
#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ #define PMAP 0xf000 /* Peripheral Mapped To This Channel */
/* Bit masks for DMACx_TCPER */ /* Bit masks for DMACx_TC_PER */
#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */ #define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */ #define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */ #define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */ #define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
/* Bit masks for DMACx_TCCNT */ /* Bit masks for DMACx_TC_CNT */
#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */ #define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */ #define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
......
arch/blackfin/mach-bf561/dma.c
View file @ 9346dba5
...@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = { ...@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
(struct dma_register *) DMA2_9_NEXT_DESC_PTR, (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
(struct dma_register *) DMA2_10_NEXT_DESC_PTR, (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
(struct dma_register *) DMA2_11_NEXT_DESC_PTR, (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR, (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR, (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR, (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR, (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR, (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR, (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR, (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR, (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR, (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
......
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