Commit 962cffbd authored by Michael Neuling's avatar Michael Neuling Committed by Benjamin Herrenschmidt

powerpc: Enforce usage of RA 0-R31 where possible

Some macros use RA where when RA=R0 the values is 0, so make this
the enforced mnemonic in the macro.

Idea suggested by Andreas Schwab.
Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent f4c01579
...@@ -231,7 +231,7 @@ ...@@ -231,7 +231,7 @@
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
__PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
...@@ -240,23 +240,23 @@ ...@@ -240,23 +240,23 @@
#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
___PPC_RB(a) | ___PPC_RS(lp)) ___PPC_RB(a) | ___PPC_RS(lp))
#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
__PPC_RA(a) | __PPC_RB(b)) __PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
__PPC_RA(a) | __PPC_RB(b)) __PPC_RA0(a) | __PPC_RB(b))
#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
__PPC_T_TLB(t) | __PPC_RA(a) | \ __PPC_T_TLB(t) | __PPC_RA0(a) | \
__PPC_RB(b)) __PPC_RB(b))
#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
__PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b)) __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
__PPC_RT(t) | __PPC_RB(b)) __PPC_RT(t) | __PPC_RB(b))
/* PASemi instructions */ /* PASemi instructions */
......
...@@ -112,7 +112,7 @@ _icswx_skip_guest: ...@@ -112,7 +112,7 @@ _icswx_skip_guest:
* a bolted entry though it will be in LRU and so will go away eventually * a bolted entry though it will be in LRU and so will go away eventually
* but let's not bother for now * but let's not bother for now
*/ */
PPC_ERATILX(0,R0,R0) PPC_ERATILX(0,0,R0)
1: 1:
blr blr
......
...@@ -903,7 +903,7 @@ skpinv: addi r6,r6,1 /* Increment */ ...@@ -903,7 +903,7 @@ skpinv: addi r6,r6,1 /* Increment */
bne 1b /* If not, repeat */ bne 1b /* If not, repeat */
/* Invalidate all TLBs */ /* Invalidate all TLBs */
PPC_TLBILX_ALL(R0,R0) PPC_TLBILX_ALL(0,R0)
sync sync
isync isync
...@@ -961,7 +961,7 @@ skpinv: addi r6,r6,1 /* Increment */ ...@@ -961,7 +961,7 @@ skpinv: addi r6,r6,1 /* Increment */
tlbwe tlbwe
/* Invalidate TLB1 */ /* Invalidate TLB1 */
PPC_TLBILX_ALL(R0,R0) PPC_TLBILX_ALL(0,R0)
sync sync
isync isync
...@@ -1020,7 +1020,7 @@ skpinv: addi r6,r6,1 /* Increment */ ...@@ -1020,7 +1020,7 @@ skpinv: addi r6,r6,1 /* Increment */
tlbwe tlbwe
/* Invalidate TLB1 */ /* Invalidate TLB1 */
PPC_TLBILX_ALL(R0,R0) PPC_TLBILX_ALL(0,R0)
sync sync
isync isync
...@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush: ...@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush:
tlbwe tlbwe
#endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
PPC_TLBILX(0,R0,R0) PPC_TLBILX(0,0,R0)
sync sync
isync isync
......
...@@ -126,7 +126,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -126,7 +126,7 @@ BEGIN_MMU_FTR_SECTION
/* Set the TLB reservation and search for existing entry. Then load /* Set the TLB reservation and search for existing entry. Then load
* the entry. * the entry.
*/ */
PPC_TLBSRX_DOT(R0,R16) PPC_TLBSRX_DOT(0,R16)
ldx r14,r14,r15 /* grab pgd entry */ ldx r14,r14,r15 /* grab pgd entry */
beq normal_tlb_miss_done /* tlb exists already, bail */ beq normal_tlb_miss_done /* tlb exists already, bail */
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
...@@ -395,7 +395,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -395,7 +395,7 @@ BEGIN_MMU_FTR_SECTION
/* Set the TLB reservation and search for existing entry. Then load /* Set the TLB reservation and search for existing entry. Then load
* the entry. * the entry.
*/ */
PPC_TLBSRX_DOT(R0,R16) PPC_TLBSRX_DOT(0,R16)
ld r14,0(r10) ld r14,0(r10)
beq normal_tlb_miss_done beq normal_tlb_miss_done
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
...@@ -528,7 +528,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -528,7 +528,7 @@ BEGIN_MMU_FTR_SECTION
/* Search if we already have a TLB entry for that virtual address, and /* Search if we already have a TLB entry for that virtual address, and
* if we do, bail out. * if we do, bail out.
*/ */
PPC_TLBSRX_DOT(R0,R16) PPC_TLBSRX_DOT(0,R16)
beq virt_page_table_tlb_miss_done beq virt_page_table_tlb_miss_done
END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV) END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
...@@ -779,7 +779,7 @@ htw_tlb_miss: ...@@ -779,7 +779,7 @@ htw_tlb_miss:
* *
* MAS1:IND should be already set based on MAS4 * MAS1:IND should be already set based on MAS4
*/ */
PPC_TLBSRX_DOT(R0,R16) PPC_TLBSRX_DOT(0,R16)
beq htw_tlb_miss_done beq htw_tlb_miss_done
/* Now, we need to walk the page tables. First check if we are in /* Now, we need to walk the page tables. First check if we are in
...@@ -919,7 +919,7 @@ tlb_load_linear: ...@@ -919,7 +919,7 @@ tlb_load_linear:
mtspr SPRN_MAS1,r15 mtspr SPRN_MAS1,r15
/* Already somebody there ? */ /* Already somebody there ? */
PPC_TLBSRX_DOT(R0,R16) PPC_TLBSRX_DOT(0,R16)
beq tlb_load_linear_done beq tlb_load_linear_done
/* Now we build the remaining MAS. MAS0 and 2 should be fine /* Now we build the remaining MAS. MAS0 and 2 should be fine
......
...@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION
andi. r3,r3,MMUCSR0_TLBFI@l andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b bne 1b
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
PPC_TLBILX_ALL(R0,R0) PPC_TLBILX_ALL(0,R0)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync msync
isync isync
...@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION
wrteei 0 wrteei 0
mfspr r4,SPRN_MAS6 /* save MAS6 */ mfspr r4,SPRN_MAS6 /* save MAS6 */
mtspr SPRN_MAS6,r3 mtspr SPRN_MAS6,r3
PPC_TLBILX_PID(R0,R0) PPC_TLBILX_PID(0,R0)
mtspr SPRN_MAS6,r4 /* restore MAS6 */ mtspr SPRN_MAS6,r4 /* restore MAS6 */
wrtee r10 wrtee r10
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
...@@ -313,7 +313,7 @@ BEGIN_MMU_FTR_SECTION ...@@ -313,7 +313,7 @@ BEGIN_MMU_FTR_SECTION
mtspr SPRN_MAS1,r4 mtspr SPRN_MAS1,r4
tlbwe tlbwe
MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE
PPC_TLBILX_VA(R0,R3) PPC_TLBILX_VA(0,R3)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync msync
isync isync
...@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid) ...@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid)
mfmsr r10 mfmsr r10
wrteei 0 wrteei 0
mtspr SPRN_MAS6,r4 mtspr SPRN_MAS6,r4
PPC_TLBILX_PID(R0,R0) PPC_TLBILX_PID(0,R0)
wrtee r10 wrtee r10
msync msync
isync isync
...@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind) ...@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind)
ori r4,r4,MAS6_SIND ori r4,r4,MAS6_SIND
wrteei 0 wrteei 0
mtspr SPRN_MAS6,r4 mtspr SPRN_MAS6,r4
PPC_TLBILX_PID(R0,R0) PPC_TLBILX_PID(0,R0)
wrtee r10 wrtee r10
msync msync
isync isync
blr blr
_GLOBAL(_tlbil_all) _GLOBAL(_tlbil_all)
PPC_TLBILX_ALL(R0,R0) PPC_TLBILX_ALL(0,R0)
msync msync
isync isync
blr blr
...@@ -364,7 +364,7 @@ _GLOBAL(_tlbil_va) ...@@ -364,7 +364,7 @@ _GLOBAL(_tlbil_va)
beq 1f beq 1f
rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
PPC_TLBILX_VA(R0,R3) PPC_TLBILX_VA(0,R3)
msync msync
isync isync
wrtee r10 wrtee r10
...@@ -379,7 +379,7 @@ _GLOBAL(_tlbivax_bcast) ...@@ -379,7 +379,7 @@ _GLOBAL(_tlbivax_bcast)
beq 1f beq 1f
rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND rlwimi r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */ 1: mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
PPC_TLBIVAX(R0,R3) PPC_TLBIVAX(0,R3)
eieio eieio
tlbsync tlbsync
sync sync
......
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