Commit 97750ceb authored by Tejun Heo's avatar Tejun Heo Committed by Jeff Garzik

libata: add @ap to ata_wait_register() and introduce ata_msleep()

Add optional @ap argument to ata_wait_register() and replace msleep()
calls with ata_msleep() which take optional @ap in addition to the
duration.  These will be used to implement EH exclusion.

This patch doesn't cause any behavior difference.
Signed-off-by: default avatarTejun Heo <tj@kernel.org>
Signed-off-by: default avatarJeff Garzik <jgarzik@redhat.com>
parent a97c4006
...@@ -567,7 +567,7 @@ int ahci_stop_engine(struct ata_port *ap) ...@@ -567,7 +567,7 @@ int ahci_stop_engine(struct ata_port *ap)
writel(tmp, port_mmio + PORT_CMD); writel(tmp, port_mmio + PORT_CMD);
/* wait for engine to stop. This could be as long as 500 msec */ /* wait for engine to stop. This could be as long as 500 msec */
tmp = ata_wait_register(port_mmio + PORT_CMD, tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
if (tmp & PORT_CMD_LIST_ON) if (tmp & PORT_CMD_LIST_ON)
return -EIO; return -EIO;
...@@ -614,7 +614,7 @@ static int ahci_stop_fis_rx(struct ata_port *ap) ...@@ -614,7 +614,7 @@ static int ahci_stop_fis_rx(struct ata_port *ap)
writel(tmp, port_mmio + PORT_CMD); writel(tmp, port_mmio + PORT_CMD);
/* wait for completion, spec says 500ms, give it 1000 */ /* wait for completion, spec says 500ms, give it 1000 */
tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
PORT_CMD_FIS_ON, 10, 1000); PORT_CMD_FIS_ON, 10, 1000);
if (tmp & PORT_CMD_FIS_ON) if (tmp & PORT_CMD_FIS_ON)
return -EBUSY; return -EBUSY;
...@@ -671,7 +671,7 @@ static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy, ...@@ -671,7 +671,7 @@ static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
readl(port_mmio + PORT_CMD); readl(port_mmio + PORT_CMD);
/* wait 10ms to be sure we've come out of LPM state */ /* wait 10ms to be sure we've come out of LPM state */
msleep(10); ata_msleep(ap, 10);
} else { } else {
cmd |= PORT_CMD_ALPE; cmd |= PORT_CMD_ALPE;
if (policy == ATA_LPM_MIN_POWER) if (policy == ATA_LPM_MIN_POWER)
...@@ -740,7 +740,7 @@ static void ahci_start_port(struct ata_port *ap) ...@@ -740,7 +740,7 @@ static void ahci_start_port(struct ata_port *ap)
emp->led_state, emp->led_state,
4); 4);
if (rc == -EBUSY) if (rc == -EBUSY)
msleep(1); ata_msleep(ap, 1);
else else
break; break;
} }
...@@ -799,7 +799,7 @@ int ahci_reset_controller(struct ata_host *host) ...@@ -799,7 +799,7 @@ int ahci_reset_controller(struct ata_host *host)
* reset must complete within 1 second, or * reset must complete within 1 second, or
* the hardware should be considered fried. * the hardware should be considered fried.
*/ */
tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET, tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
HOST_RESET, 10, 1000); HOST_RESET, 10, 1000);
if (tmp & HOST_RESET) { if (tmp & HOST_RESET) {
...@@ -1179,7 +1179,7 @@ int ahci_kick_engine(struct ata_port *ap) ...@@ -1179,7 +1179,7 @@ int ahci_kick_engine(struct ata_port *ap)
writel(tmp, port_mmio + PORT_CMD); writel(tmp, port_mmio + PORT_CMD);
rc = 0; rc = 0;
tmp = ata_wait_register(port_mmio + PORT_CMD, tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
if (tmp & PORT_CMD_CLO) if (tmp & PORT_CMD_CLO)
rc = -EIO; rc = -EIO;
...@@ -1209,8 +1209,8 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp, ...@@ -1209,8 +1209,8 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
writel(1, port_mmio + PORT_CMD_ISSUE); writel(1, port_mmio + PORT_CMD_ISSUE);
if (timeout_msec) { if (timeout_msec) {
tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1, timeout_msec); 0x1, 0x1, 1, timeout_msec);
if (tmp & 0x1) { if (tmp & 0x1) {
ahci_kick_engine(ap); ahci_kick_engine(ap);
return -EBUSY; return -EBUSY;
...@@ -1257,7 +1257,7 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class, ...@@ -1257,7 +1257,7 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
} }
/* spec says at least 5us, but be generous and sleep for 1ms */ /* spec says at least 5us, but be generous and sleep for 1ms */
msleep(1); ata_msleep(ap, 1);
/* issue the second D2H Register FIS */ /* issue the second D2H Register FIS */
tf.ctl &= ~ATA_SRST; tf.ctl &= ~ATA_SRST;
......
...@@ -3404,7 +3404,7 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline, ...@@ -3404,7 +3404,7 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline,
warned = 1; warned = 1;
} }
msleep(50); ata_msleep(link->ap, 50);
} }
} }
...@@ -3425,7 +3425,7 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline, ...@@ -3425,7 +3425,7 @@ int ata_wait_ready(struct ata_link *link, unsigned long deadline,
int ata_wait_after_reset(struct ata_link *link, unsigned long deadline, int ata_wait_after_reset(struct ata_link *link, unsigned long deadline,
int (*check_ready)(struct ata_link *link)) int (*check_ready)(struct ata_link *link))
{ {
msleep(ATA_WAIT_AFTER_RESET); ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
return ata_wait_ready(link, deadline, check_ready); return ata_wait_ready(link, deadline, check_ready);
} }
...@@ -3473,7 +3473,7 @@ int sata_link_debounce(struct ata_link *link, const unsigned long *params, ...@@ -3473,7 +3473,7 @@ int sata_link_debounce(struct ata_link *link, const unsigned long *params,
last_jiffies = jiffies; last_jiffies = jiffies;
while (1) { while (1) {
msleep(interval); ata_msleep(link->ap, interval);
if ((rc = sata_scr_read(link, SCR_STATUS, &cur))) if ((rc = sata_scr_read(link, SCR_STATUS, &cur)))
return rc; return rc;
cur &= 0xf; cur &= 0xf;
...@@ -3538,7 +3538,7 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params, ...@@ -3538,7 +3538,7 @@ int sata_link_resume(struct ata_link *link, const unsigned long *params,
* immediately after resuming. Delay 200ms before * immediately after resuming. Delay 200ms before
* debouncing. * debouncing.
*/ */
msleep(200); ata_msleep(link->ap, 200);
/* is SControl restored correctly? */ /* is SControl restored correctly? */
if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol))) if ((rc = sata_scr_read(link, SCR_CONTROL, &scontrol)))
...@@ -3742,7 +3742,7 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing, ...@@ -3742,7 +3742,7 @@ int sata_link_hardreset(struct ata_link *link, const unsigned long *timing,
/* Couldn't find anything in SATA I/II specs, but AHCI-1.1 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
* 10.4.2 says at least 1 ms. * 10.4.2 says at least 1 ms.
*/ */
msleep(1); ata_msleep(link->ap, 1);
/* bring link back */ /* bring link back */
rc = sata_link_resume(link, timing, deadline); rc = sata_link_resume(link, timing, deadline);
...@@ -6483,8 +6483,14 @@ int ata_ratelimit(void) ...@@ -6483,8 +6483,14 @@ int ata_ratelimit(void)
return __ratelimit(&ratelimit); return __ratelimit(&ratelimit);
} }
void ata_msleep(struct ata_port *ap, unsigned int msecs)
{
msleep(msecs);
}
/** /**
* ata_wait_register - wait until register value changes * ata_wait_register - wait until register value changes
* @ap: ATA port to wait register for, can be NULL
* @reg: IO-mapped register * @reg: IO-mapped register
* @mask: Mask to apply to read register value * @mask: Mask to apply to read register value
* @val: Wait condition * @val: Wait condition
...@@ -6506,7 +6512,7 @@ int ata_ratelimit(void) ...@@ -6506,7 +6512,7 @@ int ata_ratelimit(void)
* RETURNS: * RETURNS:
* The final register value. * The final register value.
*/ */
u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask, u32 val,
unsigned long interval, unsigned long timeout) unsigned long interval, unsigned long timeout)
{ {
unsigned long deadline; unsigned long deadline;
...@@ -6521,7 +6527,7 @@ u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, ...@@ -6521,7 +6527,7 @@ u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
deadline = ata_deadline(jiffies, timeout); deadline = ata_deadline(jiffies, timeout);
while ((tmp & mask) == val && time_before(jiffies, deadline)) { while ((tmp & mask) == val && time_before(jiffies, deadline)) {
msleep(interval); ata_msleep(ap, interval);
tmp = ioread32(reg); tmp = ioread32(reg);
} }
...@@ -6605,6 +6611,7 @@ EXPORT_SYMBOL_GPL(ata_std_postreset); ...@@ -6605,6 +6611,7 @@ EXPORT_SYMBOL_GPL(ata_std_postreset);
EXPORT_SYMBOL_GPL(ata_dev_classify); EXPORT_SYMBOL_GPL(ata_dev_classify);
EXPORT_SYMBOL_GPL(ata_dev_pair); EXPORT_SYMBOL_GPL(ata_dev_pair);
EXPORT_SYMBOL_GPL(ata_ratelimit); EXPORT_SYMBOL_GPL(ata_ratelimit);
EXPORT_SYMBOL_GPL(ata_msleep);
EXPORT_SYMBOL_GPL(ata_wait_register); EXPORT_SYMBOL_GPL(ata_wait_register);
EXPORT_SYMBOL_GPL(ata_scsi_queuecmd); EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
EXPORT_SYMBOL_GPL(ata_scsi_slave_config); EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
......
...@@ -779,7 +779,7 @@ void ata_port_wait_eh(struct ata_port *ap) ...@@ -779,7 +779,7 @@ void ata_port_wait_eh(struct ata_port *ap)
/* make sure SCSI EH is complete */ /* make sure SCSI EH is complete */
if (scsi_host_in_recovery(ap->scsi_host)) { if (scsi_host_in_recovery(ap->scsi_host)) {
msleep(10); ata_msleep(ap, 10);
goto retry; goto retry;
} }
} }
......
...@@ -222,7 +222,7 @@ int ata_sff_busy_sleep(struct ata_port *ap, ...@@ -222,7 +222,7 @@ int ata_sff_busy_sleep(struct ata_port *ap,
timeout = ata_deadline(timer_start, tmout_pat); timeout = ata_deadline(timer_start, tmout_pat);
while (status != 0xff && (status & ATA_BUSY) && while (status != 0xff && (status & ATA_BUSY) &&
time_before(jiffies, timeout)) { time_before(jiffies, timeout)) {
msleep(50); ata_msleep(ap, 50);
status = ata_sff_busy_wait(ap, ATA_BUSY, 3); status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
} }
...@@ -234,7 +234,7 @@ int ata_sff_busy_sleep(struct ata_port *ap, ...@@ -234,7 +234,7 @@ int ata_sff_busy_sleep(struct ata_port *ap,
timeout = ata_deadline(timer_start, tmout); timeout = ata_deadline(timer_start, tmout);
while (status != 0xff && (status & ATA_BUSY) && while (status != 0xff && (status & ATA_BUSY) &&
time_before(jiffies, timeout)) { time_before(jiffies, timeout)) {
msleep(50); ata_msleep(ap, 50);
status = ap->ops->sff_check_status(ap); status = ap->ops->sff_check_status(ap);
} }
...@@ -360,7 +360,7 @@ static void ata_dev_select(struct ata_port *ap, unsigned int device, ...@@ -360,7 +360,7 @@ static void ata_dev_select(struct ata_port *ap, unsigned int device,
if (wait) { if (wait) {
if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
msleep(150); ata_msleep(ap, 150);
ata_wait_idle(ap); ata_wait_idle(ap);
} }
} }
...@@ -1356,7 +1356,7 @@ static void ata_sff_pio_task(struct work_struct *work) ...@@ -1356,7 +1356,7 @@ static void ata_sff_pio_task(struct work_struct *work)
*/ */
status = ata_sff_busy_wait(ap, ATA_BUSY, 5); status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
if (status & ATA_BUSY) { if (status & ATA_BUSY) {
msleep(2); ata_msleep(ap, 2);
status = ata_sff_busy_wait(ap, ATA_BUSY, 10); status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
if (status & ATA_BUSY) { if (status & ATA_BUSY) {
ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE); ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
...@@ -1937,7 +1937,7 @@ int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, ...@@ -1937,7 +1937,7 @@ int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
unsigned int dev1 = devmask & (1 << 1); unsigned int dev1 = devmask & (1 << 1);
int rc, ret = 0; int rc, ret = 0;
msleep(ATA_WAIT_AFTER_RESET); ata_msleep(ap, ATA_WAIT_AFTER_RESET);
/* always check readiness of the master device */ /* always check readiness of the master device */
rc = ata_sff_wait_ready(link, deadline); rc = ata_sff_wait_ready(link, deadline);
...@@ -1966,7 +1966,7 @@ int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, ...@@ -1966,7 +1966,7 @@ int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
lbal = ioread8(ioaddr->lbal_addr); lbal = ioread8(ioaddr->lbal_addr);
if ((nsect == 1) && (lbal == 1)) if ((nsect == 1) && (lbal == 1))
break; break;
msleep(50); /* give drive a breather */ ata_msleep(ap, 50); /* give drive a breather */
} }
rc = ata_sff_wait_ready(link, deadline); rc = ata_sff_wait_ready(link, deadline);
......
...@@ -1046,7 +1046,7 @@ static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask) ...@@ -1046,7 +1046,7 @@ static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
dev1 = 0; dev1 = 0;
break; break;
} }
msleep(50); /* give drive a breather */ ata_msleep(ap, 50); /* give drive a breather */
} }
if (dev1) if (dev1)
ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
...@@ -1087,7 +1087,7 @@ static unsigned int bfin_bus_softreset(struct ata_port *ap, ...@@ -1087,7 +1087,7 @@ static unsigned int bfin_bus_softreset(struct ata_port *ap,
* *
* Old drivers/ide uses the 2mS rule and then waits for ready * Old drivers/ide uses the 2mS rule and then waits for ready
*/ */
msleep(150); ata_msleep(ap, 150);
/* Before we perform post reset processing we want to see if /* Before we perform post reset processing we want to see if
* the bus shows 0xFF because the odd clown forgets the D7 * the bus shows 0xFF because the odd clown forgets the D7
......
...@@ -322,7 +322,7 @@ static int pata_s3c_wait_after_reset(struct ata_link *link, ...@@ -322,7 +322,7 @@ static int pata_s3c_wait_after_reset(struct ata_link *link,
{ {
int rc; int rc;
msleep(ATA_WAIT_AFTER_RESET); ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
/* always check readiness of the master device */ /* always check readiness of the master device */
rc = ata_sff_wait_ready(link, deadline); rc = ata_sff_wait_ready(link, deadline);
......
...@@ -530,7 +530,7 @@ static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask, ...@@ -530,7 +530,7 @@ static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
* *
* Old drivers/ide uses the 2mS rule and then waits for ready. * Old drivers/ide uses the 2mS rule and then waits for ready.
*/ */
msleep(150); ata_msleep(ap, 150);
/* always check readiness of the master device */ /* always check readiness of the master device */
rc = ata_sff_wait_ready(link, deadline); rc = ata_sff_wait_ready(link, deadline);
...@@ -559,7 +559,7 @@ static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask, ...@@ -559,7 +559,7 @@ static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
lbal = in_be32(ioaddr->lbal_addr); lbal = in_be32(ioaddr->lbal_addr);
if ((nsect == 1) && (lbal == 1)) if ((nsect == 1) && (lbal == 1))
break; break;
msleep(50); /* give drive a breather */ ata_msleep(ap, 50); /* give drive a breather */
} }
rc = ata_sff_wait_ready(link, deadline); rc = ata_sff_wait_ready(link, deadline);
......
...@@ -678,7 +678,7 @@ static void sata_fsl_port_stop(struct ata_port *ap) ...@@ -678,7 +678,7 @@ static void sata_fsl_port_stop(struct ata_port *ap)
iowrite32(temp, hcr_base + HCONTROL); iowrite32(temp, hcr_base + HCONTROL);
/* Poll for controller to go offline - should happen immediately */ /* Poll for controller to go offline - should happen immediately */
ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
ap->private_data = NULL; ap->private_data = NULL;
dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
...@@ -729,7 +729,8 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, ...@@ -729,7 +729,8 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
iowrite32(temp, hcr_base + HCONTROL); iowrite32(temp, hcr_base + HCONTROL);
/* Poll for controller to go offline */ /* Poll for controller to go offline */
temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
1, 500);
if (temp & ONLINE) { if (temp & ONLINE) {
ata_port_printk(ap, KERN_ERR, ata_port_printk(ap, KERN_ERR,
...@@ -752,7 +753,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, ...@@ -752,7 +753,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
/* /*
* PHY reset should remain asserted for atleast 1ms * PHY reset should remain asserted for atleast 1ms
*/ */
msleep(1); ata_msleep(ap, 1);
/* /*
* Now, bring the host controller online again, this can take time * Now, bring the host controller online again, this can take time
...@@ -766,7 +767,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, ...@@ -766,7 +767,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
temp |= HCONTROL_PMP_ATTACHED; temp |= HCONTROL_PMP_ATTACHED;
iowrite32(temp, hcr_base + HCONTROL); iowrite32(temp, hcr_base + HCONTROL);
temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500); temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
if (!(temp & ONLINE)) { if (!(temp & ONLINE)) {
ata_port_printk(ap, KERN_ERR, ata_port_printk(ap, KERN_ERR,
...@@ -784,7 +785,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, ...@@ -784,7 +785,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
* presence * presence
*/ */
temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500); temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
if ((!(temp & 0x10)) || ata_link_offline(link)) { if ((!(temp & 0x10)) || ata_link_offline(link)) {
ata_port_printk(ap, KERN_WARNING, ata_port_printk(ap, KERN_WARNING,
"No Device OR PHYRDY change,Hstatus = 0x%x\n", "No Device OR PHYRDY change,Hstatus = 0x%x\n",
...@@ -797,7 +798,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, ...@@ -797,7 +798,7 @@ static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
* Wait for the first D2H from device,i.e,signature update notification * Wait for the first D2H from device,i.e,signature update notification
*/ */
start_jiffies = jiffies; start_jiffies = jiffies;
temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10, temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
500, jiffies_to_msecs(deadline - start_jiffies)); 500, jiffies_to_msecs(deadline - start_jiffies));
if ((temp & 0xFF) != 0x18) { if ((temp & 0xFF) != 0x18) {
...@@ -880,7 +881,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, ...@@ -880,7 +881,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
iowrite32(pmp, CQPMP + hcr_base); iowrite32(pmp, CQPMP + hcr_base);
iowrite32(1, CQ + hcr_base); iowrite32(1, CQ + hcr_base);
temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000); temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
if (temp & 0x1) { if (temp & 0x1) {
ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n"); ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
...@@ -896,7 +897,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, ...@@ -896,7 +897,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
goto err; goto err;
} }
msleep(1); ata_msleep(ap, 1);
/* /*
* SATA device enters reset state after receving a Control register * SATA device enters reset state after receving a Control register
...@@ -915,7 +916,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, ...@@ -915,7 +916,7 @@ static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
if (pmp != SATA_PMP_CTRL_PORT) if (pmp != SATA_PMP_CTRL_PORT)
iowrite32(pmp, CQPMP + hcr_base); iowrite32(pmp, CQPMP + hcr_base);
iowrite32(1, CQ + hcr_base); iowrite32(1, CQ + hcr_base);
msleep(150); /* ?? */ ata_msleep(ap, 150); /* ?? */
/* /*
* The above command would have signalled an interrupt on command * The above command would have signalled an interrupt on command
......
...@@ -614,7 +614,7 @@ static int inic_hardreset(struct ata_link *link, unsigned int *class, ...@@ -614,7 +614,7 @@ static int inic_hardreset(struct ata_link *link, unsigned int *class,
writew(IDMA_CTL_RST_ATA, idma_ctl); writew(IDMA_CTL_RST_ATA, idma_ctl);
readw(idma_ctl); /* flush */ readw(idma_ctl); /* flush */
msleep(1); ata_msleep(ap, 1);
writew(0, idma_ctl); writew(0, idma_ctl);
rc = sata_link_resume(link, timing, deadline); rc = sata_link_resume(link, timing, deadline);
......
...@@ -589,9 +589,9 @@ static int sil24_init_port(struct ata_port *ap) ...@@ -589,9 +589,9 @@ static int sil24_init_port(struct ata_port *ap)
sil24_clear_pmp(ap); sil24_clear_pmp(ap);
writel(PORT_CS_INIT, port + PORT_CTRL_STAT); writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
ata_wait_register(port + PORT_CTRL_STAT, ata_wait_register(ap, port + PORT_CTRL_STAT,
PORT_CS_INIT, PORT_CS_INIT, 10, 100); PORT_CS_INIT, PORT_CS_INIT, 10, 100);
tmp = ata_wait_register(port + PORT_CTRL_STAT, tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
PORT_CS_RDY, 0, 10, 100); PORT_CS_RDY, 0, 10, 100);
if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
...@@ -631,7 +631,7 @@ static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, ...@@ -631,7 +631,7 @@ static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
10, timeout_msec); 10, timeout_msec);
writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
...@@ -719,9 +719,9 @@ static int sil24_hardreset(struct ata_link *link, unsigned int *class, ...@@ -719,9 +719,9 @@ static int sil24_hardreset(struct ata_link *link, unsigned int *class,
"state, performing PORT_RST\n"); "state, performing PORT_RST\n");
writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
msleep(10); ata_msleep(ap, 10);
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
10, 5000); 10, 5000);
/* restore port configuration */ /* restore port configuration */
...@@ -740,7 +740,7 @@ static int sil24_hardreset(struct ata_link *link, unsigned int *class, ...@@ -740,7 +740,7 @@ static int sil24_hardreset(struct ata_link *link, unsigned int *class,
tout_msec = 5000; tout_msec = 5000;
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
tmp = ata_wait_register(port + PORT_CTRL_STAT, tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
tout_msec); tout_msec);
...@@ -1253,7 +1253,7 @@ static void sil24_init_controller(struct ata_host *host) ...@@ -1253,7 +1253,7 @@ static void sil24_init_controller(struct ata_host *host)
tmp = readl(port + PORT_CTRL_STAT); tmp = readl(port + PORT_CTRL_STAT);
if (tmp & PORT_CS_PORT_RST) { if (tmp & PORT_CS_PORT_RST) {
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
tmp = ata_wait_register(port + PORT_CTRL_STAT, tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
PORT_CS_PORT_RST, PORT_CS_PORT_RST,
PORT_CS_PORT_RST, 10, 100); PORT_CS_PORT_RST, 10, 100);
if (tmp & PORT_CS_PORT_RST) if (tmp & PORT_CS_PORT_RST)
......
...@@ -349,7 +349,7 @@ static int vt6420_prereset(struct ata_link *link, unsigned long deadline) ...@@ -349,7 +349,7 @@ static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
/* wait for phy to become ready, if necessary */ /* wait for phy to become ready, if necessary */
do { do {
msleep(200); ata_msleep(link->ap, 200);
svia_scr_read(link, SCR_STATUS, &sstatus); svia_scr_read(link, SCR_STATUS, &sstatus);
if ((sstatus & 0xf) != 1) if ((sstatus & 0xf) != 1)
break; break;
......
...@@ -1004,8 +1004,9 @@ extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg); ...@@ -1004,8 +1004,9 @@ extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg);
extern void ata_host_resume(struct ata_host *host); extern void ata_host_resume(struct ata_host *host);
#endif #endif
extern int ata_ratelimit(void); extern int ata_ratelimit(void);
extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, extern void ata_msleep(struct ata_port *ap, unsigned int msecs);
unsigned long interval, unsigned long timeout); extern u32 ata_wait_register(struct ata_port *ap, void __iomem *reg, u32 mask,
u32 val, unsigned long interval, unsigned long timeout);
extern int atapi_cmd_type(u8 opcode); extern int atapi_cmd_type(u8 opcode);
extern void ata_tf_to_fis(const struct ata_taskfile *tf, extern void ata_tf_to_fis(const struct ata_taskfile *tf,
u8 pmp, int is_cmd, u8 *fis); u8 pmp, int is_cmd, u8 *fis);
......
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