Commit 99a42341 authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher

drm/amd/display: Add PIXEL_RATE control regs for more instances

For use by future ASICs
Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 85cb9d50
...@@ -62,6 +62,10 @@ ...@@ -62,6 +62,10 @@
SRII(BLND_CONTROL, BLND, 4), \ SRII(BLND_CONTROL, BLND, 4), \
SRII(BLND_CONTROL, BLND, 5) SRII(BLND_CONTROL, BLND, 5)
#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
SRII(PIXEL_RATE_CNTL, blk, inst), \
SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
#define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
SRII(PIXEL_RATE_CNTL, blk, 0), \ SRII(PIXEL_RATE_CNTL, blk, 0), \
SRII(PIXEL_RATE_CNTL, blk, 1), \ SRII(PIXEL_RATE_CNTL, blk, 1), \
...@@ -151,7 +155,10 @@ ...@@ -151,7 +155,10 @@
SR(DCCG_GATE_DISABLE_CNTL2), \ SR(DCCG_GATE_DISABLE_CNTL2), \
SR(DCFCLK_CNTL),\ SR(DCFCLK_CNTL),\
SR(DCFCLK_CNTL), \ SR(DCFCLK_CNTL), \
SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
#define MMHUB_DCN_REG_LIST()\
/* todo: get these from GVM instead of reading registers ourselves */\ /* todo: get these from GVM instead of reading registers ourselves */\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
...@@ -166,10 +173,14 @@ ...@@ -166,10 +173,14 @@
MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
#define HWSEQ_DCN1_REG_LIST()\ #define HWSEQ_DCN1_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \ HWSEQ_DCN_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ MMHUB_DCN_REG_LIST(), \
HWSEQ_PHYPLL_REG_LIST(OTG), \ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
SR(DCHUBBUB_SDPIF_FB_BASE),\ SR(DCHUBBUB_SDPIF_FB_BASE),\
SR(DCHUBBUB_SDPIF_FB_OFFSET),\ SR(DCHUBBUB_SDPIF_FB_OFFSET),\
SR(DCHUBBUB_SDPIF_AGP_BASE),\ SR(DCHUBBUB_SDPIF_AGP_BASE),\
...@@ -202,8 +213,12 @@ ...@@ -202,8 +213,12 @@
#if defined(CONFIG_DRM_AMD_DC_DCN2_0) #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#define HWSEQ_DCN2_REG_LIST()\ #define HWSEQ_DCN2_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \ HWSEQ_DCN_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
HWSEQ_PHYPLL_REG_LIST(OTG), \ HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
SR(MICROSECOND_TIME_BASE_DIV), \ SR(MICROSECOND_TIME_BASE_DIV), \
SR(MILLISECOND_TIME_BASE_DIV), \ SR(MILLISECOND_TIME_BASE_DIV), \
SR(DISPCLK_FREQ_CHANGE_CNTL), \ SR(DISPCLK_FREQ_CHANGE_CNTL), \
......
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