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nexedi
linux
Commits
99ae9953
Commit
99ae9953
authored
May 21, 2009
by
Ben Dooks
Browse files
Options
Browse Files
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Plain Diff
[ARM] S3C24XX: Merge devel-gpio
Merge branch 'devel-gpio' into for-rmk-devel
parents
bcb8a0d6
7a05a2cb
Changes
38
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Showing
38 changed files
with
409 additions
and
627 deletions
+409
-627
Documentation/arm/Samsung-S3C24XX/GPIO.txt
Documentation/arm/Samsung-S3C24XX/GPIO.txt
+5
-5
arch/arm/mach-s3c2400/gpio.c
arch/arm/mach-s3c2400/gpio.c
+3
-3
arch/arm/mach-s3c2410/gpio.c
arch/arm/mach-s3c2410/gpio.c
+3
-3
arch/arm/mach-s3c2410/h1940-bluetooth.c
arch/arm/mach-s3c2410/h1940-bluetooth.c
+14
-12
arch/arm/mach-s3c2410/include/mach/gpio-core.h
arch/arm/mach-s3c2410/include/mach/gpio-core.h
+1
-1
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+103
-0
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+70
-0
arch/arm/mach-s3c2410/include/mach/gpio.h
arch/arm/mach-s3c2410/include/mach/gpio.h
+1
-0
arch/arm/mach-s3c2410/include/mach/hardware.h
arch/arm/mach-s3c2410/include/mach/hardware.h
+0
-95
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+0
-333
arch/arm/mach-s3c2410/mach-amlm5900.c
arch/arm/mach-s3c2410/mach-amlm5900.c
+3
-2
arch/arm/mach-s3c2410/mach-bast.c
arch/arm/mach-s3c2410/mach-bast.c
+5
-5
arch/arm/mach-s3c2410/mach-h1940.c
arch/arm/mach-s3c2410/mach-h1940.c
+1
-1
arch/arm/mach-s3c2410/mach-n30.c
arch/arm/mach-s3c2410/mach-n30.c
+26
-25
arch/arm/mach-s3c2410/mach-qt2410.c
arch/arm/mach-s3c2410/mach-qt2410.c
+10
-9
arch/arm/mach-s3c2410/mach-vr1000.c
arch/arm/mach-s3c2410/mach-vr1000.c
+6
-5
arch/arm/mach-s3c2410/pm.c
arch/arm/mach-s3c2410/pm.c
+3
-2
arch/arm/mach-s3c2410/usb-simtec.c
arch/arm/mach-s3c2410/usb-simtec.c
+25
-7
arch/arm/mach-s3c2412/mach-jive.c
arch/arm/mach-s3c2412/mach-jive.c
+22
-21
arch/arm/mach-s3c2412/mach-smdk2413.c
arch/arm/mach-s3c2412/mach-smdk2413.c
+5
-4
arch/arm/mach-s3c2440/mach-anubis.c
arch/arm/mach-s3c2440/mach-anubis.c
+2
-1
arch/arm/mach-s3c2440/mach-at2440evb.c
arch/arm/mach-s3c2440/mach-at2440evb.c
+1
-1
arch/arm/mach-s3c2440/mach-nexcoder.c
arch/arm/mach-s3c2440/mach-nexcoder.c
+9
-8
arch/arm/mach-s3c2440/mach-osiris.c
arch/arm/mach-s3c2440/mach-osiris.c
+5
-4
arch/arm/plat-s3c24xx/common-smdk.c
arch/arm/plat-s3c24xx/common-smdk.c
+13
-12
arch/arm/plat-s3c24xx/gpio.c
arch/arm/plat-s3c24xx/gpio.c
+9
-25
arch/arm/plat-s3c24xx/gpiolib.c
arch/arm/plat-s3c24xx/gpiolib.c
+26
-16
arch/arm/plat-s3c24xx/pm.c
arch/arm/plat-s3c24xx/pm.c
+5
-4
arch/arm/plat-s3c24xx/setup-i2c.c
arch/arm/plat-s3c24xx/setup-i2c.c
+3
-2
arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
+10
-10
arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
+10
-10
drivers/leds/leds-h1940.c
drivers/leds/leds-h1940.c
+2
-0
drivers/leds/leds-s3c24xx.c
drivers/leds/leds-s3c24xx.c
+1
-0
drivers/mmc/host/s3cmci.c
drivers/mmc/host/s3cmci.c
+2
-1
drivers/spi/spi_s3c24xx_gpio.c
drivers/spi/spi_s3c24xx_gpio.c
+1
-0
sound/soc/s3c24xx/s3c2412-i2s.c
sound/soc/s3c24xx/s3c2412-i2s.c
+1
-0
sound/soc/s3c24xx/s3c2443-ac97.c
sound/soc/s3c24xx/s3c2443-ac97.c
+1
-0
sound/soc/s3c24xx/s3c24xx-i2s.c
sound/soc/s3c24xx/s3c24xx-i2s.c
+2
-0
No files found.
Documentation/arm/Samsung-S3C24XX/GPIO.txt
View file @
99ae9953
...
...
@@ -51,7 +51,7 @@ PIN Numbers
-----------
Each pin has an unique number associated with it in regs-gpio.h,
eg S3C2410_GPA
0 or S3C2410_GPF1
. These defines are used to tell
eg S3C2410_GPA
(0) or S3C2410_GPF(1)
. These defines are used to tell
the GPIO functions which pin is to be used.
...
...
@@ -65,11 +65,11 @@ Configuring a pin
Eg:
s3c2410_gpio_cfgpin(S3C2410_GPA
0
, S3C2410_GPA0_ADDR0);
s3c2410_gpio_cfgpin(S3C2410_GPE
8
, S3C2410_GPE8_SDDAT1);
s3c2410_gpio_cfgpin(S3C2410_GPA
(0)
, S3C2410_GPA0_ADDR0);
s3c2410_gpio_cfgpin(S3C2410_GPE
(8)
, S3C2410_GPE8_SDDAT1);
which would turn GPA
0
into the lowest Address line A0, and set
GPE
8
to be connected to the SDIO/MMC controller's SDDAT1 line.
which would turn GPA
(0)
into the lowest Address line A0, and set
GPE
(8)
to be connected to the SDIO/MMC controller's SDDAT1 line.
Reading the current configuration
...
...
arch/arm/mach-s3c2400/gpio.c
View file @
99ae9953
...
...
@@ -33,10 +33,10 @@
int
s3c2400_gpio_getirq
(
unsigned
int
pin
)
{
if
(
pin
<
S3C2410_GPE
0
||
pin
>
S3C2400_GPE7_EINT7
)
return
-
1
;
/* not valid interrupts */
if
(
pin
<
S3C2410_GPE
(
0
)
||
pin
>
S3C2400_GPE
(
7
)
)
return
-
EINVAL
;
/* not valid interrupts */
return
(
pin
-
S3C2410_GPE
0
)
+
IRQ_EINT0
;
return
(
pin
-
S3C2410_GPE
(
0
)
)
+
IRQ_EINT0
;
}
EXPORT_SYMBOL
(
s3c2400_gpio_getirq
);
arch/arm/mach-s3c2410/gpio.c
View file @
99ae9953
...
...
@@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
unsigned
long
flags
;
unsigned
long
val
;
if
(
pin
<
S3C2410_GPG
8
||
pin
>
S3C2410_GPG15
)
return
-
1
;
if
(
pin
<
S3C2410_GPG
(
8
)
||
pin
>
S3C2410_GPG
(
15
)
)
return
-
EINVAL
;
config
&=
0xff
;
pin
-=
S3C2410_GPG
8
;
pin
-=
S3C2410_GPG
(
8
)
;
reg
+=
pin
&
~
3
;
local_irq_save
(
flags
);
...
...
arch/arm/mach-s3c2410/h1940-bluetooth.c
View file @
99ae9953
...
...
@@ -16,6 +16,8 @@
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <mach/h1940-latch.h>
...
...
@@ -41,9 +43,9 @@ static void h1940bt_enable(int on)
h1940_latch_control
(
0
,
H1940_LATCH_BLUETOOTH_POWER
);
/* Reset the chip */
mdelay
(
10
);
s3c2410_gpio_setpin
(
S3C2410_GPH
1
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
1
)
,
1
);
mdelay
(
10
);
s3c2410_gpio_setpin
(
S3C2410_GPH
1
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
1
)
,
0
);
state
=
1
;
}
...
...
@@ -52,9 +54,9 @@ static void h1940bt_enable(int on)
led_trigger_event
(
bt_led_trigger
,
0
);
#endif
s3c2410_gpio_setpin
(
S3C2410_GPH
1
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
1
)
,
1
);
mdelay
(
10
);
s3c2410_gpio_setpin
(
S3C2410_GPH
1
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
1
)
,
0
);
mdelay
(
10
);
h1940_latch_control
(
H1940_LATCH_BLUETOOTH_POWER
,
0
);
...
...
@@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644,
static
int
__init
h1940bt_probe
(
struct
platform_device
*
pdev
)
{
/* Configures BT serial port GPIOs */
s3c2410_gpio_cfgpin
(
S3C2410_GPH
0
,
S3C2410_GPH0_nCTS0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
0
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
1
,
S3C2410_GPH1_OUTP
);
s3c2410_gpio_pullup
(
S3C2410_GPH
1
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
2
,
S3C2410_GPH2_TXD0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
2
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
3
,
S3C2410_GPH3_RXD0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
3
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
(
0
)
,
S3C2410_GPH0_nCTS0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
(
0
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
(
1
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPH
(
1
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
(
2
)
,
S3C2410_GPH2_TXD0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
(
2
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
(
3
)
,
S3C2410_GPH3_RXD0
);
s3c2410_gpio_pullup
(
S3C2410_GPH
(
3
)
,
1
);
#ifdef CONFIG_LEDS_H1940
led_trigger_register_simple
(
"h1940-bluetooth"
,
&
bt_led_trigger
);
...
...
arch/arm/mach-s3c2410/include/mach/gpio-core.h
View file @
99ae9953
...
...
@@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct
s3c_gpio_chip
*
chip
;
if
(
pin
>
S3C2410_GPG
10
)
if
(
pin
>
S3C2410_GPG
(
10
)
)
return
NULL
;
chip
=
&
s3c24xx_gpios
[
pin
/
32
];
...
...
arch/arm/mach-s3c2410/include/mach/gpio-fns.h
0 → 100644
View file @
99ae9953
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
*
* Copyright (c) 2003,2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - hardware
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* These functions are in the to-be-removed category and it is strongly
* encouraged not to use these in new code. They will be marked deprecated
* very soon.
*
* Most of the functionality can be either replaced by the gpiocfg calls
* for the s3c platform or by the generic GPIOlib API.
*/
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
*/
extern
void
s3c2410_gpio_cfgpin
(
unsigned
int
pin
,
unsigned
int
function
);
extern
unsigned
int
s3c2410_gpio_getcfg
(
unsigned
int
pin
);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern
int
s3c2410_gpio_getirq
(
unsigned
int
pin
);
#ifdef CONFIG_CPU_S3C2400
extern
int
s3c2400_gpio_getirq
(
unsigned
int
pin
);
#endif
/* CONFIG_CPU_S3C2400 */
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
*
* on = 0 => disable filtering
* 1 => enable filtering
*
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
* width of filter (0 through 63)
*
*
*/
extern
int
s3c2410_gpio_irqfilter
(
unsigned
int
pin
,
unsigned
int
on
,
unsigned
int
config
);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
* s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
*/
extern
void
s3c2410_gpio_pullup
(
unsigned
int
pin
,
unsigned
int
to
);
/* s3c2410_gpio_getpull
*
* Read the state of the pull-up on a given pin
*
* return:
* < 0 => error code
* 0 => enabled
* 1 => disabled
*/
extern
int
s3c2410_gpio_getpull
(
unsigned
int
pin
);
extern
void
s3c2410_gpio_setpin
(
unsigned
int
pin
,
unsigned
int
to
);
extern
unsigned
int
s3c2410_gpio_getpin
(
unsigned
int
pin
);
arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
View file @
99ae9953
...
...
@@ -11,6 +11,9 @@
* published by the Free Software Foundation.
*/
#ifndef __MACH_GPIONRS_H
#define __MACH_GPIONRS_H
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
...
...
@@ -21,3 +24,70 @@
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7)
/* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32)
#define S3C2410_GPIO_C_NR (32)
#define S3C2410_GPIO_D_NR (32)
#define S3C2410_GPIO_E_NR (32)
#define S3C2410_GPIO_F_NR (32)
#define S3C2410_GPIO_G_NR (32)
#define S3C2410_GPIO_H_NR (32)
#if CONFIG_S3C_GPIO_SPACE != 0
#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment
#endif
#define S3C2410_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0)
#ifndef __ASSEMBLY__
enum
s3c_gpio_number
{
S3C2410_GPIO_A_START
=
0
,
S3C2410_GPIO_B_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_A
),
S3C2410_GPIO_C_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_B
),
S3C2410_GPIO_D_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_C
),
S3C2410_GPIO_E_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_D
),
S3C2410_GPIO_F_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_E
),
S3C2410_GPIO_G_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_F
),
S3C2410_GPIO_H_START
=
S3C2410_GPIO_NEXT
(
S3C2410_GPIO_G
),
};
#endif
/* __ASSEMBLY__ */
/* S3C2410 GPIO number definitions. */
#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr))
#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr))
#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr))
#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr))
#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr))
#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr))
#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr))
#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr))
/* compatibility until drivers can be modified */
#define S3C2410_GPA0 S3C2410_GPA(0)
#define S3C2410_GPA1 S3C2410_GPA(1)
#define S3C2410_GPA3 S3C2410_GPA(3)
#define S3C2410_GPA7 S3C2410_GPA(7)
#define S3C2410_GPE0 S3C2410_GPE(0)
#define S3C2410_GPE1 S3C2410_GPE(1)
#define S3C2410_GPE2 S3C2410_GPE(2)
#define S3C2410_GPE3 S3C2410_GPE(3)
#define S3C2410_GPE4 S3C2410_GPE(4)
#define S3C2410_GPE5 S3C2410_GPE(5)
#define S3C2410_GPE6 S3C2410_GPE(6)
#define S3C2410_GPE7 S3C2410_GPE(7)
#define S3C2410_GPE8 S3C2410_GPE(8)
#define S3C2410_GPE9 S3C2410_GPE(9)
#define S3C2410_GPE10 S3C2410_GPE(10)
#define S3C2410_GPH10 S3C2410_GPH(10)
#endif
/* __MACH_GPIONRS_H */
arch/arm/mach-s3c2410/include/mach/gpio.h
View file @
99ae9953
...
...
@@ -24,5 +24,6 @@
#include <asm-generic/gpio.h>
#include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h>
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
arch/arm/mach-s3c2410/include/mach/hardware.h
View file @
99ae9953
...
...
@@ -15,101 +15,6 @@
#ifndef __ASSEMBLY__
/* external functions for GPIO support
*
* These allow various different clients to access the same GPIO
* registers without conflicting. If your driver only owns the entire
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
*/
/* s3c2410_gpio_cfgpin
*
* set the configuration of the given pin to the value passed.
*
* eg:
* s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
* s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
*/
extern
void
s3c2410_gpio_cfgpin
(
unsigned
int
pin
,
unsigned
int
function
);
extern
unsigned
int
s3c2410_gpio_getcfg
(
unsigned
int
pin
);
/* s3c2410_gpio_getirq
*
* turn the given pin number into the corresponding IRQ number
*
* returns:
* < 0 = no interrupt for this pin
* >=0 = interrupt number for the pin
*/
extern
int
s3c2410_gpio_getirq
(
unsigned
int
pin
);
/* s3c2410_gpio_irq2pin
*
* turn the given irq number into the corresponding GPIO number
*
* returns:
* < 0 = no pin
* >=0 = gpio pin number
*/
extern
int
s3c2410_gpio_irq2pin
(
unsigned
int
irq
);
#ifdef CONFIG_CPU_S3C2400
extern
int
s3c2400_gpio_getirq
(
unsigned
int
pin
);
#endif
/* CONFIG_CPU_S3C2400 */
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
*
* on = 0 => disable filtering
* 1 => enable filtering
*
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
* width of filter (0 through 63)
*
*
*/
extern
int
s3c2410_gpio_irqfilter
(
unsigned
int
pin
,
unsigned
int
on
,
unsigned
int
config
);
/* s3c2410_gpio_pullup
*
* configure the pull-up control on the given pin
*
* to = 1 => disable the pull-up
* 0 => enable the pull-up
*
* eg;
*
* s3c2410_gpio_pullup(S3C2410_GPB0, 0);
* s3c2410_gpio_pullup(S3C2410_GPE8, 0);
*/
extern
void
s3c2410_gpio_pullup
(
unsigned
int
pin
,
unsigned
int
to
);
/* s3c2410_gpio_getpull
*
* Read the state of the pull-up on a given pin
*
* return:
* < 0 => error code
* 0 => enabled
* 1 => disabled
*/
extern
int
s3c2410_gpio_getpull
(
unsigned
int
pin
);
extern
void
s3c2410_gpio_setpin
(
unsigned
int
pin
,
unsigned
int
to
);
extern
unsigned
int
s3c2410_gpio_getpin
(
unsigned
int
pin
);
extern
unsigned
int
s3c2410_modify_misccr
(
unsigned
int
clr
,
unsigned
int
chg
);
#ifdef CONFIG_CPU_S3C2440
...
...
arch/arm/mach-s3c2410/include/mach/regs-gpio.h
View file @
99ae9953
...
...
@@ -69,104 +69,58 @@
#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
#define S3C2410_GPA0_OUT (0<<0)
#define S3C2410_GPA0_ADDR0 (1<<0)
#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
#define S3C2410_GPA1_OUT (0<<1)
#define S3C2410_GPA1_ADDR16 (1<<1)
#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
#define S3C2410_GPA2_OUT (0<<2)
#define S3C2410_GPA2_ADDR17 (1<<2)
#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
#define S3C2410_GPA3_OUT (0<<3)
#define S3C2410_GPA3_ADDR18 (1<<3)
#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
#define S3C2410_GPA4_OUT (0<<4)
#define S3C2410_GPA4_ADDR19 (1<<4)
#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
#define S3C2410_GPA5_OUT (0<<5)
#define S3C2410_GPA5_ADDR20 (1<<5)
#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
#define S3C2410_GPA6_OUT (0<<6)
#define S3C2410_GPA6_ADDR21 (1<<6)
#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
#define S3C2410_GPA7_OUT (0<<7)
#define S3C2410_GPA7_ADDR22 (1<<7)
#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
#define S3C2410_GPA8_OUT (0<<8)
#define S3C2410_GPA8_ADDR23 (1<<8)
#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
#define S3C2410_GPA9_OUT (0<<9)
#define S3C2410_GPA9_ADDR24 (1<<9)
#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
#define S3C2410_GPA10_OUT (0<<10)
#define S3C2410_GPA10_ADDR25 (1<<10)
#define S3C2400_GPA10_SCKE (1<<10)
#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
#define S3C2410_GPA11_OUT (0<<11)
#define S3C2410_GPA11_ADDR26 (1<<11)
#define S3C2400_GPA11_nCAS0 (1<<11)
#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
#define S3C2410_GPA12_OUT (0<<12)
#define S3C2410_GPA12_nGCS1 (1<<12)
#define S3C2400_GPA12_nCAS1 (1<<12)
#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
#define S3C2410_GPA13_OUT (0<<13)
#define S3C2410_GPA13_nGCS2 (1<<13)
#define S3C2400_GPA13_nGCS1 (1<<13)
#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
#define S3C2410_GPA14_OUT (0<<14)
#define S3C2410_GPA14_nGCS3 (1<<14)
#define S3C2400_GPA14_nGCS2 (1<<14)
#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
#define S3C2410_GPA15_OUT (0<<15)
#define S3C2410_GPA15_nGCS4 (1<<15)
#define S3C2400_GPA15_nGCS3 (1<<15)
#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
#define S3C2410_GPA16_OUT (0<<16)
#define S3C2410_GPA16_nGCS5 (1<<16)
#define S3C2400_GPA16_nGCS4 (1<<16)
#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
#define S3C2410_GPA17_OUT (0<<17)
#define S3C2410_GPA17_CLE (1<<17)
#define S3C2400_GPA17_nGCS5 (1<<17)
#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
#define S3C2410_GPA18_OUT (0<<18)
#define S3C2410_GPA18_ALE (1<<18)
#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
#define S3C2410_GPA19_OUT (0<<19)
#define S3C2410_GPA19_nFWE (1<<19)
#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
#define S3C2410_GPA20_OUT (0<<20)
#define S3C2410_GPA20_nFRE (1<<20)
#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
#define S3C2410_GPA21_OUT (0<<21)
#define S3C2410_GPA21_nRSTOUT (1<<21)
#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
#define S3C2410_GPA22_OUT (0<<22)
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved on S3C2410 */
...
...
@@ -194,107 +148,69 @@
/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
#define S3C2410_GPB0_INP (0x00 << 0)
#define S3C2410_GPB0_OUTP (0x01 << 0)
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
#define S3C2400_GPB0_DATA16 (0x02 << 0)
#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
#define S3C2410_GPB1_INP (0x00 << 2)
#define S3C2410_GPB1_OUTP (0x01 << 2)
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
#define S3C2400_GPB1_DATA17 (0x02 << 2)
#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
#define S3C2410_GPB2_INP (0x00 << 4)
#define S3C2410_GPB2_OUTP (0x01 << 4)
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
#define S3C2400_GPB2_DATA18 (0x02 << 4)
#define S3C2400_GPB2_TCLK1 (0x03 << 4)
#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
#define S3C2410_GPB3_INP (0x00 << 6)
#define S3C2410_GPB3_OUTP (0x01 << 6)
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
#define S3C2400_GPB3_DATA19 (0x02 << 6)
#define S3C2400_GPB3_TXD1 (0x03 << 6)
#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
#define S3C2410_GPB4_INP (0x00 << 8)
#define S3C2410_GPB4_OUTP (0x01 << 8)
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
#define S3C2400_GPB4_DATA20 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8)
#define S3C2400_GPB4_RXD1 (0x03 << 8)
#define S3C2400_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
#define S3C2410_GPB5_INP (0x00 << 10)
#define S3C2410_GPB5_OUTP (0x01 << 10)
#define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2443_GPB5_XBACK (0x03 << 10)
#define S3C2400_GPB5_DATA21 (0x02 << 10)
#define S3C2400_GPB5_nCTS1 (0x03 << 10)
#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
#define S3C2410_GPB6_INP (0x00 << 12)
#define S3C2410_GPB6_OUTP (0x01 << 12)
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2443_GPB6_XBREQ (0x03 << 12)
#define S3C2400_GPB6_DATA22 (0x02 << 12)
#define S3C2400_GPB6_nRTS1 (0x03 << 12)
#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
#define S3C2410_GPB7_INP (0x00 << 14)
#define S3C2410_GPB7_OUTP (0x01 << 14)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1 (0x03 << 14)
#define S3C2400_GPB7_DATA23 (0x02 << 14)
#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
#define S3C2410_GPB8_INP (0x00 << 16)
#define S3C2410_GPB8_OUTP (0x01 << 16)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
#define S3C2400_GPB8_DATA24 (0x02 << 16)
#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
#define S3C2410_GPB9_INP (0x00 << 18)
#define S3C2410_GPB9_OUTP (0x01 << 18)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0 (0x03 << 18)
#define S3C2400_GPB9_DATA25 (0x02 << 18)
#define S3C2400_GPB9_I2SSDI (0x03 << 18)
#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
#define S3C2410_GPB10_INP (0x00 << 20)
#define S3C2410_GPB10_OUTP (0x01 << 20)
#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
#define S3C2400_GPB10_DATA26 (0x02 << 20)
#define S3C2400_GPB10_nSS (0x03 << 20)
#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
#define S3C2400_GPB11_INP (0x00 << 22)
#define S3C2400_GPB11_OUTP (0x01 << 22)
#define S3C2400_GPB11_DATA27 (0x02 << 22)
#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
#define S3C2400_GPB12_INP (0x00 << 24)
#define S3C2400_GPB12_OUTP (0x01 << 24)
#define S3C2400_GPB12_DATA28 (0x02 << 24)
#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
#define S3C2400_GPB13_INP (0x00 << 26)
#define S3C2400_GPB13_OUTP (0x01 << 26)
#define S3C2400_GPB13_DATA29 (0x02 << 26)
#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
#define S3C2400_GPB14_INP (0x00 << 28)
#define S3C2400_GPB14_OUTP (0x01 << 28)
#define S3C2400_GPB14_DATA30 (0x02 << 28)
#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
#define S3C2400_GPB15_INP (0x00 << 30)
#define S3C2400_GPB15_OUTP (0x01 << 30)
#define S3C2400_GPB15_DATA31 (0x02 << 30)
...
...
@@ -315,99 +231,51 @@
#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
#define S3C2410_GPC0_INP (0x00 << 0)
#define S3C2410_GPC0_OUTP (0x01 << 0)
#define S3C2410_GPC0_LEND (0x02 << 0)
#define S3C2400_GPC0_VD0 (0x02 << 0)
#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
#define S3C2410_GPC1_INP (0x00 << 2)
#define S3C2410_GPC1_OUTP (0x01 << 2)
#define S3C2410_GPC1_VCLK (0x02 << 2)
#define S3C2400_GPC1_VD1 (0x02 << 2)
#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
#define S3C2410_GPC2_INP (0x00 << 4)
#define S3C2410_GPC2_OUTP (0x01 << 4)
#define S3C2410_GPC2_VLINE (0x02 << 4)
#define S3C2400_GPC2_VD2 (0x02 << 4)
#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
#define S3C2410_GPC3_INP (0x00 << 6)
#define S3C2410_GPC3_OUTP (0x01 << 6)
#define S3C2410_GPC3_VFRAME (0x02 << 6)
#define S3C2400_GPC3_VD3 (0x02 << 6)
#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
#define S3C2410_GPC4_INP (0x00 << 8)
#define S3C2410_GPC4_OUTP (0x01 << 8)
#define S3C2410_GPC4_VM (0x02 << 8)
#define S3C2400_GPC4_VD4 (0x02 << 8)
#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
#define S3C2410_GPC5_INP (0x00 << 10)
#define S3C2410_GPC5_OUTP (0x01 << 10)
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
#define S3C2400_GPC5_VD5 (0x02 << 10)
#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
#define S3C2410_GPC6_INP (0x00 << 12)
#define S3C2410_GPC6_OUTP (0x01 << 12)
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
#define S3C2400_GPC6_VD6 (0x02 << 12)
#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
#define S3C2410_GPC7_INP (0x00 << 14)
#define S3C2410_GPC7_OUTP (0x01 << 14)
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
#define S3C2400_GPC7_VD7 (0x02 << 14)
#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
#define S3C2410_GPC8_INP (0x00 << 16)
#define S3C2410_GPC8_OUTP (0x01 << 16)
#define S3C2410_GPC8_VD0 (0x02 << 16)
#define S3C2400_GPC8_VD8 (0x02 << 16)
#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
#define S3C2410_GPC9_INP (0x00 << 18)
#define S3C2410_GPC9_OUTP (0x01 << 18)
#define S3C2410_GPC9_VD1 (0x02 << 18)
#define S3C2400_GPC9_VD9 (0x02 << 18)
#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
#define S3C2410_GPC10_INP (0x00 << 20)
#define S3C2410_GPC10_OUTP (0x01 << 20)
#define S3C2410_GPC10_VD2 (0x02 << 20)
#define S3C2400_GPC10_VD10 (0x02 << 20)
#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
#define S3C2410_GPC11_INP (0x00 << 22)
#define S3C2410_GPC11_OUTP (0x01 << 22)
#define S3C2410_GPC11_VD3 (0x02 << 22)
#define S3C2400_GPC11_VD11 (0x02 << 22)
#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
#define S3C2410_GPC12_INP (0x00 << 24)
#define S3C2410_GPC12_OUTP (0x01 << 24)
#define S3C2410_GPC12_VD4 (0x02 << 24)
#define S3C2400_GPC12_VD12 (0x02 << 24)
#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
#define S3C2410_GPC13_INP (0x00 << 26)
#define S3C2410_GPC13_OUTP (0x01 << 26)
#define S3C2410_GPC13_VD5 (0x02 << 26)
#define S3C2400_GPC13_VD13 (0x02 << 26)
#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
#define S3C2410_GPC14_INP (0x00 << 28)
#define S3C2410_GPC14_OUTP (0x01 << 28)
#define S3C2410_GPC14_VD6 (0x02 << 28)
#define S3C2400_GPC14_VD14 (0x02 << 28)
#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
#define S3C2410_GPC15_INP (0x00 << 30)
#define S3C2410_GPC15_OUTP (0x01 << 30)
#define S3C2410_GPC15_VD7 (0x02 << 30)
#define S3C2400_GPC15_VD15 (0x02 << 30)
...
...
@@ -432,99 +300,51 @@
#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
#define S3C2410_GPD0_INP (0x00 << 0)
#define S3C2410_GPD0_OUTP (0x01 << 0)
#define S3C2410_GPD0_VD8 (0x02 << 0)
#define S3C2400_GPD0_VFRAME (0x02 << 0)
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
#define S3C2410_GPD1_INP (0x00 << 2)
#define S3C2410_GPD1_OUTP (0x01 << 2)
#define S3C2410_GPD1_VD9 (0x02 << 2)
#define S3C2400_GPD1_VM (0x02 << 2)
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
#define S3C2410_GPD2_INP (0x00 << 4)
#define S3C2410_GPD2_OUTP (0x01 << 4)
#define S3C2410_GPD2_VD10 (0x02 << 4)
#define S3C2400_GPD2_VLINE (0x02 << 4)
#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
#define S3C2410_GPD3_INP (0x00 << 6)
#define S3C2410_GPD3_OUTP (0x01 << 6)
#define S3C2410_GPD3_VD11 (0x02 << 6)
#define S3C2400_GPD3_VCLK (0x02 << 6)
#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
#define S3C2410_GPD4_INP (0x00 << 8)
#define S3C2410_GPD4_OUTP (0x01 << 8)
#define S3C2410_GPD4_VD12 (0x02 << 8)
#define S3C2400_GPD4_LEND (0x02 << 8)
#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
#define S3C2410_GPD5_INP (0x00 << 10)
#define S3C2410_GPD5_OUTP (0x01 << 10)
#define S3C2410_GPD5_VD13 (0x02 << 10)
#define S3C2400_GPD5_TOUT0 (0x02 << 10)
#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
#define S3C2410_GPD6_INP (0x00 << 12)
#define S3C2410_GPD6_OUTP (0x01 << 12)
#define S3C2410_GPD6_VD14 (0x02 << 12)
#define S3C2400_GPD6_TOUT1 (0x02 << 12)
#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
#define S3C2410_GPD7_INP (0x00 << 14)
#define S3C2410_GPD7_OUTP (0x01 << 14)
#define S3C2410_GPD7_VD15 (0x02 << 14)
#define S3C2400_GPD7_TOUT2 (0x02 << 14)
#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
#define S3C2410_GPD8_INP (0x00 << 16)
#define S3C2410_GPD8_OUTP (0x01 << 16)
#define S3C2410_GPD8_VD16 (0x02 << 16)
#define S3C2400_GPD8_TOUT3 (0x02 << 16)
#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
#define S3C2410_GPD9_INP (0x00 << 18)
#define S3C2410_GPD9_OUTP (0x01 << 18)
#define S3C2410_GPD9_VD17 (0x02 << 18)
#define S3C2400_GPD9_TCLK0 (0x02 << 18)
#define S3C2410_GPD9_MASK (0x03 << 18)
#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
#define S3C2410_GPD10_INP (0x00 << 20)
#define S3C2410_GPD10_OUTP (0x01 << 20)
#define S3C2410_GPD10_VD18 (0x02 << 20)
#define S3C2400_GPD10_nWAIT (0x02 << 20)
#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
#define S3C2410_GPD11_INP (0x00 << 22)
#define S3C2410_GPD11_OUTP (0x01 << 22)
#define S3C2410_GPD11_VD19 (0x02 << 22)
#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
#define S3C2410_GPD12_INP (0x00 << 24)
#define S3C2410_GPD12_OUTP (0x01 << 24)
#define S3C2410_GPD12_VD20 (0x02 << 24)
#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
#define S3C2410_GPD13_INP (0x00 << 26)
#define S3C2410_GPD13_OUTP (0x01 << 26)
#define S3C2410_GPD13_VD21 (0x02 << 26)
#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
#define S3C2410_GPD14_INP (0x00 << 28)
#define S3C2410_GPD14_OUTP (0x01 << 28)
#define S3C2410_GPD14_VD22 (0x02 << 28)
#define S3C2410_GPD14_nSS1 (0x03 << 28)
#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
#define S3C2410_GPD15_INP (0x00 << 30)
#define S3C2410_GPD15_OUTP (0x01 << 30)
#define S3C2410_GPD15_VD23 (0x02 << 30)
#define S3C2410_GPD15_nSS0 (0x03 << 30)
...
...
@@ -550,34 +370,22 @@
#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
#define S3C2410_GPE0_INP (0x00 << 0)
#define S3C2410_GPE0_OUTP (0x01 << 0)
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
#define S3C2400_GPE0_EINT0 (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
#define S3C2410_GPE1_INP (0x00 << 2)
#define S3C2410_GPE1_OUTP (0x01 << 2)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
#define S3C2400_GPE1_EINT1 (0x02 << 2)
#define S3C2400_GPE1_nSS (0x03 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
#define S3C2410_GPE2_INP (0x00 << 4)
#define S3C2410_GPE2_OUTP (0x01 << 4)
#define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
#define S3C2400_GPE2_EINT2 (0x02 << 4)
#define S3C2400_GPE2_I2SSDI (0x03 << 4)
#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
#define S3C2410_GPE3_INP (0x00 << 6)
#define S3C2410_GPE3_OUTP (0x01 << 6)
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2443_GPE3_AC_SDI (0x03 << 6)
#define S3C2400_GPE3_EINT3 (0x02 << 6)
...
...
@@ -585,9 +393,6 @@
#define S3C2410_GPE3_nSS0 (0x03 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
#define S3C2410_GPE4_INP (0x00 << 8)
#define S3C2410_GPE4_OUTP (0x01 << 8)
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2443_GPE4_AC_SDO (0x03 << 8)
#define S3C2400_GPE4_EINT4 (0x02 << 8)
...
...
@@ -595,81 +400,48 @@
#define S3C2410_GPE4_I2SSDI (0x03 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
#define S3C2410_GPE5_INP (0x00 << 10)
#define S3C2410_GPE5_OUTP (0x01 << 10)
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
#define S3C2400_GPE5_EINT5 (0x02 << 10)
#define S3C2400_GPE5_TCLK1 (0x03 << 10)
#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
#define S3C2410_GPE6_INP (0x00 << 12)
#define S3C2410_GPE6_OUTP (0x01 << 12)
#define S3C2410_GPE6_SDCMD (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
#define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
#define S3C2400_GPE6_EINT6 (0x02 << 12)
#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
#define S3C2410_GPE7_INP (0x00 << 14)
#define S3C2410_GPE7_OUTP (0x01 << 14)
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
#define S3C2443_GPE7_AC_SDI (0x03 << 14)
#define S3C2400_GPE7_EINT7 (0x02 << 14)
#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
#define S3C2410_GPE8_INP (0x00 << 16)
#define S3C2410_GPE8_OUTP (0x01 << 16)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
#define S3C2443_GPE8_AC_SDO (0x03 << 16)
#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
#define S3C2410_GPE9_INP (0x00 << 18)
#define S3C2410_GPE9_OUTP (0x01 << 18)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
#define S3C2443_GPE9_AC_SYNC (0x03 << 18)
#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
#define S3C2400_GPE9_nXBACK (0x03 << 18)
#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
#define S3C2410_GPE10_INP (0x00 << 20)
#define S3C2410_GPE10_OUTP (0x01 << 20)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
#define S3C2443_GPE10_AC_nRESET (0x03 << 20)
#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
#define S3C2410_GPE11_INP (0x00 << 22)
#define S3C2410_GPE11_OUTP (0x01 << 22)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
#define S3C2400_GPE11_nXBREQ (0x03 << 22)
#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
#define S3C2410_GPE12_INP (0x00 << 24)
#define S3C2410_GPE12_OUTP (0x01 << 24)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
#define S3C2410_GPE13_INP (0x00 << 26)
#define S3C2410_GPE13_OUTP (0x01 << 26)
#define S3C2410_GPE13_SPICLK0 (0x02 << 26)
#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
#define S3C2410_GPE14_INP (0x00 << 28)
#define S3C2410_GPE14_OUTP (0x01 << 28)
#define S3C2410_GPE14_IICSCL (0x02 << 28)
#define S3C2410_GPE14_MASK (0x03 << 28)
#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
#define S3C2410_GPE15_INP (0x00 << 30)
#define S3C2410_GPE15_OUTP (0x01 << 30)
#define S3C2410_GPE15_IICSDA (0x02 << 30)
#define S3C2410_GPE15_MASK (0x03 << 30)
...
...
@@ -705,55 +477,31 @@
#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
#define S3C2410_GPF0_INP (0x00 << 0)
#define S3C2410_GPF0_OUTP (0x01 << 0)
#define S3C2410_GPF0_EINT0 (0x02 << 0)
#define S3C2400_GPF0_RXD0 (0x02 << 0)
#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
#define S3C2410_GPF1_INP (0x00 << 2)
#define S3C2410_GPF1_OUTP (0x01 << 2)
#define S3C2410_GPF1_EINT1 (0x02 << 2)
#define S3C2400_GPF1_RXD1 (0x02 << 2)
#define S3C2400_GPF1_IICSDA (0x03 << 2)
#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
#define S3C2410_GPF2_INP (0x00 << 4)
#define S3C2410_GPF2_OUTP (0x01 << 4)
#define S3C2410_GPF2_EINT2 (0x02 << 4)
#define S3C2400_GPF2_TXD0 (0x02 << 4)
#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
#define S3C2410_GPF3_INP (0x00 << 6)
#define S3C2410_GPF3_OUTP (0x01 << 6)
#define S3C2410_GPF3_EINT3 (0x02 << 6)
#define S3C2400_GPF3_TXD1 (0x02 << 6)
#define S3C2400_GPF3_IICSCL (0x03 << 6)
#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
#define S3C2410_GPF4_INP (0x00 << 8)
#define S3C2410_GPF4_OUTP (0x01 << 8)
#define S3C2410_GPF4_EINT4 (0x02 << 8)
#define S3C2400_GPF4_nRTS0 (0x02 << 8)
#define S3C2400_GPF4_nXBACK (0x03 << 8)
#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
#define S3C2410_GPF5_INP (0x00 << 10)
#define S3C2410_GPF5_OUTP (0x01 << 10)
#define S3C2410_GPF5_EINT5 (0x02 << 10)
#define S3C2400_GPF5_nCTS0 (0x02 << 10)
#define S3C2400_GPF5_nXBREQ (0x03 << 10)
#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
#define S3C2410_GPF6_INP (0x00 << 12)
#define S3C2410_GPF6_OUTP (0x01 << 12)
#define S3C2410_GPF6_EINT6 (0x02 << 12)
#define S3C2400_GPF6_CLKOUT (0x02 << 12)
#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
#define S3C2410_GPF7_INP (0x00 << 14)
#define S3C2410_GPF7_OUTP (0x01 << 14)
#define S3C2410_GPF7_EINT7 (0x02 << 14)
#define S3C2410_GPF_PUPDIS(x) (1<<(x))
...
...
@@ -778,117 +526,69 @@
#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
#define S3C2410_GPG0_INP (0x00 << 0)
#define S3C2410_GPG0_OUTP (0x01 << 0)
#define S3C2410_GPG0_EINT8 (0x02 << 0)
#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
#define S3C2410_GPG1_INP (0x00 << 2)
#define S3C2410_GPG1_OUTP (0x01 << 2)
#define S3C2410_GPG1_EINT9 (0x02 << 2)
#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
#define S3C2410_GPG2_INP (0x00 << 4)
#define S3C2410_GPG2_OUTP (0x01 << 4)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG2_nSS0 (0x03 << 4)
#define S3C2400_GPG2_CDCLK (0x02 << 4)
#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
#define S3C2410_GPG3_INP (0x00 << 6)
#define S3C2410_GPG3_OUTP (0x01 << 6)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG3_nSS1 (0x03 << 6)
#define S3C2400_GPG3_I2SSDO (0x02 << 6)
#define S3C2400_GPG3_I2SSDI (0x03 << 6)
#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
#define S3C2410_GPG4_INP (0x00 << 8)
#define S3C2410_GPG4_OUTP (0x01 << 8)
#define S3C2410_GPG4_EINT12 (0x02 << 8)
#define S3C2400_GPG4_MMCCLK (0x02 << 8)
#define S3C2400_GPG4_I2SSDI (0x03 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
#define S3C2410_GPG5_INP (0x00 << 10)
#define S3C2410_GPG5_OUTP (0x01 << 10)
#define S3C2410_GPG5_EINT13 (0x02 << 10)
#define S3C2400_GPG5_MMCCMD (0x02 << 10)
#define S3C2400_GPG5_IICSDA (0x03 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
/* not s3c2443 */
#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
#define S3C2410_GPG6_INP (0x00 << 12)
#define S3C2410_GPG6_OUTP (0x01 << 12)
#define S3C2410_GPG6_EINT14 (0x02 << 12)
#define S3C2400_GPG6_MMCDAT (0x02 << 12)
#define S3C2400_GPG6_IICSCL (0x03 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
#define S3C2410_GPG7_INP (0x00 << 14)
#define S3C2410_GPG7_OUTP (0x01 << 14)
#define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
#define S3C2400_GPG7_SPIMISO (0x02 << 14)
#define S3C2400_GPG7_IICSDA (0x03 << 14)
#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
#define S3C2410_GPG8_INP (0x00 << 16)
#define S3C2410_GPG8_OUTP (0x01 << 16)
#define S3C2410_GPG8_EINT16 (0x02 << 16)
#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
#define S3C2400_GPG8_IICSCL (0x03 << 16)
#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
#define S3C2410_GPG9_INP (0x00 << 18)
#define S3C2410_GPG9_OUTP (0x01 << 18)
#define S3C2410_GPG9_EINT17 (0x02 << 18)
#define S3C2400_GPG9_SPICLK (0x02 << 18)
#define S3C2400_GPG9_MMCCLK (0x03 << 18)
#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
#define S3C2410_GPG10_INP (0x00 << 20)
#define S3C2410_GPG10_OUTP (0x01 << 20)
#define S3C2410_GPG10_EINT18 (0x02 << 20)
#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
#define S3C2410_GPG11_INP (0x00 << 22)
#define S3C2410_GPG11_OUTP (0x01 << 22)
#define S3C2410_GPG11_EINT19 (0x02 << 22)
#define S3C2410_GPG11_TCLK1 (0x03 << 22)
#define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
#define S3C2410_GPG12_INP (0x00 << 24)
#define S3C2410_GPG12_OUTP (0x01 << 24)
#define S3C2410_GPG12_EINT20 (0x02 << 24)
#define S3C2410_GPG12_XMON (0x03 << 24)
#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
#define S3C2443_GPG12_nINPACK (0x03 << 24)
#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
#define S3C2410_GPG13_INP (0x00 << 26)
#define S3C2410_GPG13_OUTP (0x01 << 26)
#define S3C2410_GPG13_EINT21 (0x02 << 26)
#define S3C2410_GPG13_nXPON (0x03 << 26)
#define S3C2443_GPG13_CF_nREG (0x03 << 26)
#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
#define S3C2410_GPG14_INP (0x00 << 28)
#define S3C2410_GPG14_OUTP (0x01 << 28)
#define S3C2410_GPG14_EINT22 (0x02 << 28)
#define S3C2410_GPG14_YMON (0x03 << 28)
#define S3C2443_GPG14_CF_RESET (0x03 << 28)
#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
#define S3C2410_GPG15_INP (0x00 << 30)
#define S3C2410_GPG15_OUTP (0x01 << 30)
#define S3C2410_GPG15_EINT23 (0x02 << 30)
#define S3C2410_GPG15_nYPON (0x03 << 30)
#define S3C2443_GPG15_CF_PWR (0x03 << 30)
...
...
@@ -907,62 +607,29 @@
#define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
#define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
#define S3C2410_GPH0_INP (0x00 << 0)
#define S3C2410_GPH0_OUTP (0x01 << 0)
#define S3C2410_GPH0_nCTS0 (0x02 << 0)
#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
#define S3C2410_GPH1_INP (0x00 << 2)
#define S3C2410_GPH1_OUTP (0x01 << 2)
#define S3C2410_GPH1_nRTS0 (0x02 << 2)
#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
#define S3C2410_GPH2_INP (0x00 << 4)
#define S3C2410_GPH2_OUTP (0x01 << 4)
#define S3C2410_GPH2_TXD0 (0x02 << 4)
#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
#define S3C2410_GPH3_INP (0x00 << 6)
#define S3C2410_GPH3_OUTP (0x01 << 6)
#define S3C2410_GPH3_RXD0 (0x02 << 6)
#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
#define S3C2410_GPH4_INP (0x00 << 8)
#define S3C2410_GPH4_OUTP (0x01 << 8)
#define S3C2410_GPH4_TXD1 (0x02 << 8)
#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
#define S3C2410_GPH5_INP (0x00 << 10)
#define S3C2410_GPH5_OUTP (0x01 << 10)
#define S3C2410_GPH5_RXD1 (0x02 << 10)
#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
#define S3C2410_GPH6_INP (0x00 << 12)
#define S3C2410_GPH6_OUTP (0x01 << 12)
#define S3C2410_GPH6_TXD2 (0x02 << 12)
#define S3C2410_GPH6_nRTS1 (0x03 << 12)
#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
#define S3C2410_GPH7_INP (0x00 << 14)
#define S3C2410_GPH7_OUTP (0x01 << 14)
#define S3C2410_GPH7_RXD2 (0x02 << 14)
#define S3C2410_GPH7_nCTS1 (0x03 << 14)
#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
#define S3C2410_GPH8_INP (0x00 << 16)
#define S3C2410_GPH8_OUTP (0x01 << 16)
#define S3C2410_GPH8_UCLK (0x02 << 16)
#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
#define S3C2410_GPH9_INP (0x00 << 18)
#define S3C2410_GPH9_OUTP (0x01 << 18)
#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
#define S3C2410_GPH10_INP (0x00 << 20)
#define S3C2410_GPH10_OUTP (0x01 << 20)
#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
/* The S3C2412 and S3C2413 move the GPJ register set to after
...
...
arch/arm/mach-s3c2410/mach-amlm5900.c
View file @
99ae9953
...
...
@@ -32,6 +32,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/proc_fs.h>
...
...
@@ -224,8 +225,8 @@ static void amlm5900_init_pm(void)
}
else
{
enable_irq_wake
(
IRQ_EINT9
);
/* configure the suspend/resume status pin */
s3c2410_gpio_cfgpin
(
S3C2410_GPF
2
,
S3C2410_GPF2_OUTP
);
s3c2410_gpio_pullup
(
S3C2410_GPF
2
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
2
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPF
(
2
)
,
0
);
}
}
static
void
__init
amlm5900_init
(
void
)
...
...
arch/arm/mach-s3c2410/mach-bast.c
View file @
99ae9953
...
...
@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
...
...
@@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
static
int
bast_pm_suspend
(
struct
sys_device
*
sd
,
pm_message_t
state
)
{
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin
(
S3C2410_GPA
21
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
21
,
S3C2410_GPA21_O
UT
);
s3c2410_gpio_setpin
(
S3C2410_GPA
(
21
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
(
21
),
S3C2410_GPIO_OUTP
UT
);
return
0
;
}
static
int
bast_pm_resume
(
struct
sys_device
*
sd
)
{
s3c2410_gpio_cfgpin
(
S3C2410_GPA
21
,
S3C2410_GPA21_nRSTOUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
(
21
)
,
S3C2410_GPA21_nRSTOUT
);
return
0
;
}
...
...
@@ -593,8 +594,6 @@ static void __init bast_map_io(void)
s3c24xx_init_io
(
bast_iodesc
,
ARRAY_SIZE
(
bast_iodesc
));
s3c24xx_init_clocks
(
0
);
s3c24xx_init_uarts
(
bast_uartcfgs
,
ARRAY_SIZE
(
bast_uartcfgs
));
usb_simtec_init
();
}
static
void
__init
bast_init
(
void
)
...
...
@@ -608,6 +607,7 @@ static void __init bast_init(void)
i2c_register_board_info
(
0
,
bast_i2c_devs
,
ARRAY_SIZE
(
bast_i2c_devs
));
usb_simtec_init
();
nor_simtec_init
();
}
...
...
arch/arm/mach-s3c2410/mach-h1940.c
View file @
99ae9953
...
...
@@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd)
static
struct
s3c2410_udc_mach_info
h1940_udc_cfg
__initdata
=
{
.
udc_command
=
h1940_udc_pullup
,
.
vbus_pin
=
S3C2410_GPG
5
,
.
vbus_pin
=
S3C2410_GPG
(
5
)
,
.
vbus_pin_inverted
=
1
,
};
...
...
arch/arm/mach-s3c2410/mach-n30.c
View file @
99ae9953
...
...
@@ -19,6 +19,7 @@
#include <linux/gpio_keys.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
...
...
@@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
{
switch
(
cmd
)
{
case
S3C2410_UDC_P_ENABLE
:
s3c2410_gpio_setpin
(
S3C2410_GPB
3
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
3
)
,
1
);
break
;
case
S3C2410_UDC_P_DISABLE
:
s3c2410_gpio_setpin
(
S3C2410_GPB
3
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
3
)
,
0
);
break
;
case
S3C2410_UDC_P_RESET
:
break
;
...
...
@@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
static
struct
s3c2410_udc_mach_info
n30_udc_cfg
__initdata
=
{
.
udc_command
=
n30_udc_pullup
,
.
vbus_pin
=
S3C2410_GPG
1
,
.
vbus_pin
=
S3C2410_GPG
(
1
)
,
.
vbus_pin_inverted
=
0
,
};
static
struct
gpio_keys_button
n30_buttons
[]
=
{
{
.
gpio
=
S3C2410_GPF
0
,
.
gpio
=
S3C2410_GPF
(
0
)
,
.
code
=
KEY_POWER
,
.
desc
=
"Power"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
9
,
.
gpio
=
S3C2410_GPG
(
9
)
,
.
code
=
KEY_UP
,
.
desc
=
"Thumbwheel Up"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
8
,
.
gpio
=
S3C2410_GPG
(
8
)
,
.
code
=
KEY_DOWN
,
.
desc
=
"Thumbwheel Down"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
7
,
.
gpio
=
S3C2410_GPG
(
7
)
,
.
code
=
KEY_ENTER
,
.
desc
=
"Thumbwheel Press"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
7
,
.
gpio
=
S3C2410_GPF
(
7
)
,
.
code
=
KEY_HOMEPAGE
,
.
desc
=
"Home"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
6
,
.
gpio
=
S3C2410_GPF
(
6
)
,
.
code
=
KEY_CALENDAR
,
.
desc
=
"Calendar"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
5
,
.
gpio
=
S3C2410_GPF
(
5
)
,
.
code
=
KEY_ADDRESSBOOK
,
.
desc
=
"Contacts"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
4
,
.
gpio
=
S3C2410_GPF
(
4
)
,
.
code
=
KEY_MAIL
,
.
desc
=
"Mail"
,
.
active_low
=
0
,
...
...
@@ -169,73 +170,73 @@ static struct platform_device n30_button_device = {
static
struct
gpio_keys_button
n35_buttons
[]
=
{
{
.
gpio
=
S3C2410_GPF
0
,
.
gpio
=
S3C2410_GPF
(
0
)
,
.
code
=
KEY_POWER
,
.
desc
=
"Power"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
9
,
.
gpio
=
S3C2410_GPG
(
9
)
,
.
code
=
KEY_UP
,
.
desc
=
"Joystick Up"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
8
,
.
gpio
=
S3C2410_GPG
(
8
)
,
.
code
=
KEY_DOWN
,
.
desc
=
"Joystick Down"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
6
,
.
gpio
=
S3C2410_GPG
(
6
)
,
.
code
=
KEY_DOWN
,
.
desc
=
"Joystick Left"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
5
,
.
gpio
=
S3C2410_GPG
(
5
)
,
.
code
=
KEY_DOWN
,
.
desc
=
"Joystick Right"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
7
,
.
gpio
=
S3C2410_GPG
(
7
)
,
.
code
=
KEY_ENTER
,
.
desc
=
"Joystick Press"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
7
,
.
gpio
=
S3C2410_GPF
(
7
)
,
.
code
=
KEY_HOMEPAGE
,
.
desc
=
"Home"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
6
,
.
gpio
=
S3C2410_GPF
(
6
)
,
.
code
=
KEY_CALENDAR
,
.
desc
=
"Calendar"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
5
,
.
gpio
=
S3C2410_GPF
(
5
)
,
.
code
=
KEY_ADDRESSBOOK
,
.
desc
=
"Contacts"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
4
,
.
gpio
=
S3C2410_GPF
(
4
)
,
.
code
=
KEY_MAIL
,
.
desc
=
"Mail"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPF
3
,
.
gpio
=
S3C2410_GPF
(
3
)
,
.
code
=
SW_RADIO
,
.
desc
=
"GPS Antenna"
,
.
active_low
=
0
,
},
{
.
gpio
=
S3C2410_GPG
2
,
.
gpio
=
S3C2410_GPG
(
2
)
,
.
code
=
SW_HEADPHONE_INSERT
,
.
desc
=
"Headphone"
,
.
active_low
=
0
,
...
...
@@ -259,7 +260,7 @@ static struct platform_device n35_button_device = {
/* This is the bluetooth LED on the device. */
static
struct
s3c24xx_led_platdata
n30_blue_led_pdata
=
{
.
name
=
"blue_led"
,
.
gpio
=
S3C2410_GPG
6
,
.
gpio
=
S3C2410_GPG
(
6
)
,
.
def_trigger
=
""
,
};
...
...
@@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
static
struct
s3c24xx_led_platdata
n30_warning_led_pdata
=
{
.
name
=
"warning_led"
,
.
flags
=
S3C24XX_LEDF_ACTLOW
,
.
gpio
=
S3C2410_GPD
9
,
.
gpio
=
S3C2410_GPD
(
9
)
,
.
def_trigger
=
""
,
};
...
...
arch/arm/mach-s3c2410/mach-qt2410.c
View file @
99ae9953
...
...
@@ -27,6 +27,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
...
...
@@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = {
/* LED */
static
struct
s3c24xx_led_platdata
qt2410_pdata_led
=
{
.
gpio
=
S3C2410_GPB
0
,
.
gpio
=
S3C2410_GPB
(
0
)
,
.
flags
=
S3C24XX_LEDF_ACTLOW
|
S3C24XX_LEDF_TRISTATE
,
.
name
=
"led"
,
.
def_trigger
=
"timer"
,
...
...
@@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
{
switch
(
cs
)
{
case
BITBANG_CS_ACTIVE
:
s3c2410_gpio_setpin
(
S3C2410_GPB
5
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
5
)
,
0
);
break
;
case
BITBANG_CS_INACTIVE
:
s3c2410_gpio_setpin
(
S3C2410_GPB
5
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
5
)
,
1
);
break
;
}
}
static
struct
s3c2410_spigpio_info
spi_gpio_cfg
=
{
.
pin_clk
=
S3C2410_GPG
7
,
.
pin_mosi
=
S3C2410_GPG
6
,
.
pin_miso
=
S3C2410_GPG
5
,
.
pin_clk
=
S3C2410_GPG
(
7
)
,
.
pin_mosi
=
S3C2410_GPG
(
6
)
,
.
pin_miso
=
S3C2410_GPG
(
5
)
,
.
chip_select
=
&
spi_gpio_cs
,
};
...
...
@@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void)
}
s3c24xx_fb_set_platdata
(
&
qt2410_fb_info
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
0
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
0
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
(
0
)
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
0
)
,
1
);
s3c24xx_udc_set_platdata
(
&
qt2410_udc_cfg
);
s3c_i2c0_set_platdata
(
NULL
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
5
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
(
5
)
,
S3C2410_GPIO_OUTPUT
);
platform_add_devices
(
qt2410_devices
,
ARRAY_SIZE
(
qt2410_devices
));
s3c_pm_init
();
...
...
arch/arm/mach-s3c2410/mach-vr1000.c
View file @
99ae9953
...
...
@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/dm9000.h>
#include <linux/i2c.h>
...
...
@@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = {
static
struct
s3c24xx_led_platdata
vr1000_led1_pdata
=
{
.
name
=
"led1"
,
.
gpio
=
S3C2410_GPB
0
,
.
gpio
=
S3C2410_GPB
(
0
)
,
.
def_trigger
=
""
,
};
static
struct
s3c24xx_led_platdata
vr1000_led2_pdata
=
{
.
name
=
"led2"
,
.
gpio
=
S3C2410_GPB
1
,
.
gpio
=
S3C2410_GPB
(
1
)
,
.
def_trigger
=
""
,
};
static
struct
s3c24xx_led_platdata
vr1000_led3_pdata
=
{
.
name
=
"led3"
,
.
gpio
=
S3C2410_GPB
2
,
.
gpio
=
S3C2410_GPB
(
2
)
,
.
def_trigger
=
""
,
};
...
...
@@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = {
static
void
vr1000_power_off
(
void
)
{
s3c2410_gpio_cfgpin
(
S3C2410_GPB
9
,
S3C2410_GPB9_OUTP
);
s3c2410_gpio_setpin
(
S3C2410_GPB
9
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
(
9
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
9
)
,
1
);
}
static
void
__init
vr1000_map_io
(
void
)
...
...
arch/arm/mach-s3c2410/pm.c
View file @
99ae9953
...
...
@@ -25,6 +25,7 @@
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/sysdev.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/hardware.h>
...
...
@@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void)
}
if
(
machine_is_aml_m5900
()
)
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
1
);
}
...
...
@@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev)
__raw_writel
(
tmp
,
S3C2410_GSTATUS2
);
if
(
machine_is_aml_m5900
()
)
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
0
);
return
0
;
}
...
...
arch/arm/mach-s3c2410/usb-simtec.c
View file @
99ae9953
...
...
@@ -18,9 +18,11 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
...
...
@@ -29,7 +31,6 @@
#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <asm/irq.h>
...
...
@@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to)
power_state
[
port
]
=
to
;
if
(
power_state
[
0
]
&&
power_state
[
1
])
s3c2410_gpio_setpin
(
S3C2410_GPB4
,
0
);
gpio_set_value
(
S3C2410_GPB
(
4
)
,
0
);
else
s3c2410_gpio_setpin
(
S3C2410_GPB4
,
1
);
gpio_set_value
(
S3C2410_GPB
(
4
)
,
1
);
}
static
irqreturn_t
...
...
@@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw)
{
struct
s3c2410_hcd_info
*
info
=
pw
;
if
(
s3c2410_gpio_getpin
(
S3C2410_GPG10
)
==
0
)
{
if
(
gpio_get_value
(
S3C2410_GPG
(
10
)
)
==
0
)
{
pr_debug
(
"usb_simtec: over-current irq (oc detected)
\n
"
);
s3c2410_usb_report_oc
(
info
,
3
);
}
else
{
...
...
@@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = {
int
usb_simtec_init
(
void
)
{
int
ret
;
printk
(
"USB Power Control, (c) 2004 Simtec Electronics
\n
"
);
s3c_device_usb
.
dev
.
platform_data
=
&
usb_simtec_info
;
s3c2410_gpio_cfgpin
(
S3C2410_GPB4
,
S3C2410_GPB4_OUTP
);
s3c2410_gpio_setpin
(
S3C2410_GPB4
,
1
);
ret
=
gpio_request
(
S3C2410_GPB
(
4
),
"USB power control"
);
if
(
ret
<
0
)
{
pr_err
(
"%s: failed to get GPB4
\n
"
,
__func__
);
return
ret
;
}
ret
=
gpio_request
(
S3C2410_GPG
(
10
),
"USB overcurrent"
);
if
(
ret
<
0
)
{
pr_err
(
"%s: failed to get GPG10
\n
"
,
__func__
);
gpio_free
(
S3C2410_GPB
(
4
));
return
ret
;
}
/* turn power on */
gpio_direction_output
(
S3C2410_GPB
(
4
),
1
);
gpio_direction_input
(
S3C2410_GPG
(
10
));
s3c_device_usb
.
dev
.
platform_data
=
&
usb_simtec_info
;
return
0
;
}
arch/arm/mach-s3c2412/mach-jive.c
View file @
99ae9953
...
...
@@ -16,6 +16,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
...
...
@@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set)
{
printk
(
KERN_DEBUG
"%s(%d)
\n
"
,
__func__
,
set
);
s3c2410_gpio_setpin
(
S3C2410_GPG
13
,
set
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
13
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPG
(
13
)
,
set
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
13
)
,
S3C2410_GPIO_OUTPUT
);
}
#undef LCD_UPPER_MARGIN
...
...
@@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = {
static
void
jive_lcd_spi_chipselect
(
struct
s3c2410_spigpio_info
*
spi
,
int
cs
)
{
s3c2410_gpio_setpin
(
S3C2410_GPB
7
,
cs
?
0
:
1
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
7
)
,
cs
?
0
:
1
);
}
static
struct
s3c2410_spigpio_info
jive_lcd_spi
=
{
.
bus_num
=
1
,
.
pin_clk
=
S3C2410_GPG
8
,
.
pin_mosi
=
S3C2410_GPB
8
,
.
pin_clk
=
S3C2410_GPG
(
8
)
,
.
pin_mosi
=
S3C2410_GPB
(
8
)
,
.
num_chipselect
=
1
,
.
chip_select
=
jive_lcd_spi_chipselect
,
};
...
...
@@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = {
static
void
jive_wm8750_chipselect
(
struct
s3c2410_spigpio_info
*
spi
,
int
cs
)
{
s3c2410_gpio_setpin
(
S3C2410_GPH
10
,
cs
?
0
:
1
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
10
)
,
cs
?
0
:
1
);
}
static
struct
s3c2410_spigpio_info
jive_wm8750_spi
=
{
.
bus_num
=
2
,
.
pin_clk
=
S3C2410_GPB
4
,
.
pin_mosi
=
S3C2410_GPB
9
,
.
pin_clk
=
S3C2410_GPB
(
4
)
,
.
pin_mosi
=
S3C2410_GPB
(
9
)
,
.
num_chipselect
=
1
,
.
chip_select
=
jive_wm8750_chipselect
,
};
...
...
@@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = {
};
static
struct
s3c2410_udc_mach_info
jive_udc_cfg
__initdata
=
{
.
vbus_pin
=
S3C2410_GPG
1
,
/* detect is on GPG1 */
.
vbus_pin
=
S3C2410_GPG
(
1
)
,
/* detect is on GPG1 */
};
/* Jive power management device */
...
...
@@ -529,8 +530,8 @@ static void jive_power_off(void)
{
printk
(
KERN_INFO
"powering system down...
\n
"
);
s3c2410_gpio_setpin
(
S3C2410_GPC
5
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPC
5
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPC
(
5
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPC
(
5
)
,
S3C2410_GPIO_OUTPUT
);
}
static
void
__init
jive_machine_init
(
void
)
...
...
@@ -634,22 +635,22 @@ static void __init jive_machine_init(void)
/* initialise the spi */
s3c2410_gpio_setpin
(
S3C2410_GPG
13
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
13
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPG
(
13
)
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
13
)
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
7
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
7
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
7
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
(
7
)
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
6
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
6
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPB
(
6
)
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPB
(
6
)
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPG
8
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
8
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPG
(
8
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
8
)
,
S3C2410_GPIO_OUTPUT
);
/* initialise the WM8750 spi */
s3c2410_gpio_setpin
(
S3C2410_GPH
10
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
10
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPH
(
10
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPH
(
10
)
,
S3C2410_GPIO_OUTPUT
);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
...
...
arch/arm/mach-s3c2412/mach-smdk2413.c
View file @
99ae9953
...
...
@@ -17,6 +17,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
...
...
@@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd)
switch
(
cmd
)
{
case
S3C2410_UDC_P_ENABLE
:
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
1
);
break
;
case
S3C2410_UDC_P_DISABLE
:
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
0
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
0
);
break
;
case
S3C2410_UDC_P_RESET
:
break
;
...
...
@@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void)
{
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
2
,
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
2
)
,
S3C2410_GPIO_OUTPUT
);
s3c2410_modify_misccr
(
S3C2410_MISCCR_USBHOST
|
S3C2410_MISCCR_USBSUSPND0
|
...
...
arch/arm/mach-s3c2440/mach-anubis.c
View file @
99ae9953
...
...
@@ -15,6 +15,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
...
...
@@ -468,7 +469,7 @@ static void __init anubis_map_io(void)
anubis_nand_sets
[
0
].
nr_partitions
=
ARRAY_SIZE
(
anubis_default_nand_part_large
);
}
else
{
/* ensure that the GPIO is setup */
s3c2410_gpio_setpin
(
S3C2410_GPA
0
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPA
(
0
)
,
1
);
}
}
...
...
arch/arm/mach-s3c2440/mach-at2440evb.c
View file @
99ae9953
...
...
@@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = {
};
static
struct
s3c24xx_mci_pdata
at2440evb_mci_pdata
=
{
.
gpio_detect
=
S3C2410_GPG
10
,
.
gpio_detect
=
S3C2410_GPG
(
10
)
,
};
/* 7" LCD panel */
...
...
arch/arm/mach-s3c2440/mach-nexcoder.c
View file @
99ae9953
...
...
@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/string.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
...
...
@@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = {
static
void
__init
nexcoder_sensorboard_init
(
void
)
{
// Initialize SCCB bus
s3c2410_gpio_setpin
(
S3C2410_GPE
14
,
1
);
// IICSCL
s3c2410_gpio_cfgpin
(
S3C2410_GPE
14
,
S3C2410_GPE14_OUTP
);
s3c2410_gpio_setpin
(
S3C2410_GPE
15
,
1
);
// IICSDA
s3c2410_gpio_cfgpin
(
S3C2410_GPE
15
,
S3C2410_GPE15_OUTP
);
s3c2410_gpio_setpin
(
S3C2410_GPE
(
14
)
,
1
);
// IICSCL
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
14
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPE
(
15
)
,
1
);
// IICSDA
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
15
),
S3C2410_GPIO_OUTPUT
);
// Power up the sensor board
s3c2410_gpio_setpin
(
S3C2410_GPF
1
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
1
,
S3C2410_GPF1_OUTP
);
// CAM_GPIO7 => nLDO_PWRDN
s3c2410_gpio_setpin
(
S3C2410_GPF
2
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
2
,
S3C2410_GPF2_OUTP
);
// CAM_GPIO6 => CAM_PWRDN
s3c2410_gpio_setpin
(
S3C2410_GPF
(
1
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
1
),
S3C2410_GPIO_OUTPUT
);
// CAM_GPIO7 => nLDO_PWRDN
s3c2410_gpio_setpin
(
S3C2410_GPF
(
2
)
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
2
),
S3C2410_GPIO_OUTPUT
);
// CAM_GPIO6 => CAM_PWRDN
}
static
void
__init
nexcoder_map_io
(
void
)
...
...
arch/arm/mach-s3c2440/mach-osiris.c
View file @
99ae9953
...
...
@@ -15,6 +15,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
...
...
@@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state)
__raw_writeb
(
tmp
,
OSIRIS_VA_CTRL0
);
/* ensure that an nRESET is not generated on resume. */
s3c2410_gpio_setpin
(
S3C2410_GPA
21
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
21
,
S3C2410_GPA21_O
UT
);
s3c2410_gpio_setpin
(
S3C2410_GPA
(
21
)
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
(
21
),
S3C2410_GPIO_OUTP
UT
);
return
0
;
}
...
...
@@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd)
__raw_writeb
(
pm_osiris_ctrl0
,
OSIRIS_VA_CTRL0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
21
,
S3C2410_GPA21_nRSTOUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPA
(
21
)
,
S3C2410_GPA21_nRSTOUT
);
return
0
;
}
...
...
@@ -384,7 +385,7 @@ static void __init osiris_map_io(void)
osiris_nand_sets
[
0
].
nr_partitions
=
ARRAY_SIZE
(
osiris_default_nand_part_large
);
}
else
{
/* write-protect line to the NAND */
s3c2410_gpio_setpin
(
S3C2410_GPA
0
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPA
(
0
)
,
1
);
}
/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
...
...
arch/arm/plat-s3c24xx/common-smdk.c
View file @
99ae9953
...
...
@@ -18,6 +18,7 @@
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/platform_device.h>
...
...
@@ -47,27 +48,27 @@
/* LED devices */
static
struct
s3c24xx_led_platdata
smdk_pdata_led4
=
{
.
gpio
=
S3C2410_GPF
4
,
.
gpio
=
S3C2410_GPF
(
4
)
,
.
flags
=
S3C24XX_LEDF_ACTLOW
|
S3C24XX_LEDF_TRISTATE
,
.
name
=
"led4"
,
.
def_trigger
=
"timer"
,
};
static
struct
s3c24xx_led_platdata
smdk_pdata_led5
=
{
.
gpio
=
S3C2410_GPF
5
,
.
gpio
=
S3C2410_GPF
(
5
)
,
.
flags
=
S3C24XX_LEDF_ACTLOW
|
S3C24XX_LEDF_TRISTATE
,
.
name
=
"led5"
,
.
def_trigger
=
"nand-disk"
,
};
static
struct
s3c24xx_led_platdata
smdk_pdata_led6
=
{
.
gpio
=
S3C2410_GPF
6
,
.
gpio
=
S3C2410_GPF
(
6
)
,
.
flags
=
S3C24XX_LEDF_ACTLOW
|
S3C24XX_LEDF_TRISTATE
,
.
name
=
"led6"
,
};
static
struct
s3c24xx_led_platdata
smdk_pdata_led7
=
{
.
gpio
=
S3C2410_GPF
7
,
.
gpio
=
S3C2410_GPF
(
7
)
,
.
flags
=
S3C24XX_LEDF_ACTLOW
|
S3C24XX_LEDF_TRISTATE
,
.
name
=
"led7"
,
};
...
...
@@ -184,15 +185,15 @@ void __init smdk_machine_init(void)
{
/* Configure the LEDs (even if we have no LED support)*/
s3c2410_gpio_cfgpin
(
S3C2410_GPF
4
,
S3C2410_GPF4_OUTP
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
5
,
S3C2410_GPF5_OUTP
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
6
,
S3C2410_GPF6_OUTP
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
7
,
S3C2410_GPF7_OUTP
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
4
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
5
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
6
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPF
(
7
),
S3C2410_GPIO_OUTPUT
);
s3c2410_gpio_setpin
(
S3C2410_GPF
4
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
5
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
6
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
7
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
4
)
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
5
)
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
6
)
,
1
);
s3c2410_gpio_setpin
(
S3C2410_GPF
(
7
)
,
1
);
if
(
machine_is_smdk2443
())
smdk_nand_info
.
twrph0
=
50
;
...
...
arch/arm/plat-s3c24xx/gpio.c
View file @
99ae9953
...
...
@@ -183,35 +183,19 @@ EXPORT_SYMBOL(s3c2410_modify_misccr);
int
s3c2410_gpio_getirq
(
unsigned
int
pin
)
{
if
(
pin
<
S3C2410_GPF
0
||
pin
>
S3C2410_GPG15
)
return
-
1
;
/* not valid interrupts */
if
(
pin
<
S3C2410_GPF
(
0
)
||
pin
>
S3C2410_GPG
(
15
)
)
return
-
EINVAL
;
/* not valid interrupts */
if
(
pin
<
S3C2410_GPG
0
&&
pin
>
S3C2410_GPF7
)
return
-
1
;
/* not valid pin */
if
(
pin
<
S3C2410_GPG
(
0
)
&&
pin
>
S3C2410_GPF
(
7
)
)
return
-
EINVAL
;
/* not valid pin */
if
(
pin
<
S3C2410_GPF
4
)
return
(
pin
-
S3C2410_GPF
0
)
+
IRQ_EINT0
;
if
(
pin
<
S3C2410_GPF
(
4
)
)
return
(
pin
-
S3C2410_GPF
(
0
)
)
+
IRQ_EINT0
;
if
(
pin
<
S3C2410_GPG
0
)
return
(
pin
-
S3C2410_GPF
4
)
+
IRQ_EINT4
;
if
(
pin
<
S3C2410_GPG
(
0
)
)
return
(
pin
-
S3C2410_GPF
(
4
)
)
+
IRQ_EINT4
;
return
(
pin
-
S3C2410_GPG
0
)
+
IRQ_EINT8
;
return
(
pin
-
S3C2410_GPG
(
0
)
)
+
IRQ_EINT8
;
}
EXPORT_SYMBOL
(
s3c2410_gpio_getirq
);
int
s3c2410_gpio_irq2pin
(
unsigned
int
irq
)
{
if
(
irq
>=
IRQ_EINT0
&&
irq
<=
IRQ_EINT3
)
return
S3C2410_GPF0
+
(
irq
-
IRQ_EINT0
);
if
(
irq
>=
IRQ_EINT4
&&
irq
<=
IRQ_EINT7
)
return
S3C2410_GPF4
+
(
irq
-
IRQ_EINT4
);
if
(
irq
>=
IRQ_EINT8
&&
irq
<=
IRQ_EINT23
)
return
S3C2410_GPG0
+
(
irq
-
IRQ_EINT8
);
return
-
EINVAL
;
}
EXPORT_SYMBOL
(
s3c2410_gpio_irq2pin
);
arch/arm/plat-s3c24xx/gpiolib.c
View file @
99ae9953
...
...
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/gpio.h>
...
...
@@ -78,10 +79,10 @@ static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
struct
s3c_gpio_chip
s3c24xx_gpios
[]
=
{
[
0
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPA0
)
,
.
base
=
S3C24
10_GPACON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_1bit
),
.
chip
=
{
.
base
=
S3C2410_GPA
0
,
.
base
=
S3C2410_GPA
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOA"
,
.
ngpio
=
24
,
...
...
@@ -90,50 +91,50 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
},
[
1
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPB0
)
,
.
base
=
S3C24
10_GPBCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPB
0
,
.
base
=
S3C2410_GPB
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOB"
,
.
ngpio
=
16
,
},
},
[
2
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPC0
)
,
.
base
=
S3C24
10_GPCCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPC
0
,
.
base
=
S3C2410_GPC
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOC"
,
.
ngpio
=
16
,
},
},
[
3
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPD0
)
,
.
base
=
S3C24
10_GPDCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPD
0
,
.
base
=
S3C2410_GPD
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOD"
,
.
ngpio
=
16
,
},
},
[
4
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPE0
)
,
.
base
=
S3C24
10_GPECON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPE
0
,
.
base
=
S3C2410_GPE
(
0
)
,
.
label
=
"GPIOE"
,
.
owner
=
THIS_MODULE
,
.
ngpio
=
16
,
},
},
[
5
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPF0
)
,
.
base
=
S3C24
10_GPFCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPF
0
,
.
base
=
S3C2410_GPF
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOF"
,
.
ngpio
=
8
,
...
...
@@ -141,15 +142,24 @@ struct s3c_gpio_chip s3c24xx_gpios[] = {
},
},
[
6
]
=
{
.
base
=
S3C24
XX_GPIO_BASE
(
S3C2410_GPG0
)
,
.
base
=
S3C24
10_GPGCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPG
0
,
.
base
=
S3C2410_GPG
(
0
)
,
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOG"
,
.
ngpio
=
1
0
,
.
ngpio
=
1
6
,
.
to_irq
=
s3c24xx_gpiolib_bankg_toirq
,
},
},
{
.
base
=
S3C2410_GPHCON
,
.
pm
=
__gpio_pm
(
&
s3c_gpio_pm_2bit
),
.
chip
=
{
.
base
=
S3C2410_GPH
(
0
),
.
owner
=
THIS_MODULE
,
.
label
=
"GPIOH"
,
.
ngpio
=
11
,
},
},
};
...
...
@@ -164,4 +174,4 @@ static __init int s3c24xx_gpiolib_init(void)
return
0
;
}
arch
_initcall
(
s3c24xx_gpiolib_init
);
core
_initcall
(
s3c24xx_gpiolib_init
);
arch/arm/plat-s3c24xx/pm.c
View file @
99ae9953
...
...
@@ -30,6 +30,7 @@
#include <linux/suspend.h>
#include <linux/errno.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/io.h>
...
...
@@ -123,12 +124,12 @@ void s3c_pm_configure_extint(void)
* and then configure it as an input if it is not
*/
for
(
pin
=
S3C2410_GPF
0
;
pin
<=
S3C2410_GPF7
;
pin
++
)
{
s3c_pm_check_resume_pin
(
pin
,
pin
-
S3C2410_GPF
0
);
for
(
pin
=
S3C2410_GPF
(
0
);
pin
<=
S3C2410_GPF
(
7
)
;
pin
++
)
{
s3c_pm_check_resume_pin
(
pin
,
pin
-
S3C2410_GPF
(
0
)
);
}
for
(
pin
=
S3C2410_GPG
0
;
pin
<=
S3C2410_GPG7
;
pin
++
)
{
s3c_pm_check_resume_pin
(
pin
,
(
pin
-
S3C2410_GPG
0
)
+
8
);
for
(
pin
=
S3C2410_GPG
(
0
);
pin
<=
S3C2410_GPG
(
7
)
;
pin
++
)
{
s3c_pm_check_resume_pin
(
pin
,
(
pin
-
S3C2410_GPG
(
0
)
)
+
8
);
}
}
...
...
arch/arm/plat-s3c24xx/setup-i2c.c
View file @
99ae9953
...
...
@@ -11,6 +11,7 @@
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
struct
platform_device
;
...
...
@@ -20,6 +21,6 @@ struct platform_device;
void
s3c_i2c0_cfg_gpio
(
struct
platform_device
*
dev
)
{
s3c2410_gpio_cfgpin
(
S3C2410_GPE
15
,
S3C2410_GPE15_IICSDA
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
14
,
S3C2410_GPE14_IICSCL
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
15
)
,
S3C2410_GPE15_IICSDA
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
14
)
,
S3C2410_GPE14_IICSCL
);
}
arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c
View file @
99ae9953
...
...
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
int
enable
)
{
if
(
enable
)
{
s3c2410_gpio_cfgpin
(
S3C2410_GPE
13
,
S3C2410_GPE13_SPICLK0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
12
,
S3C2410_GPE12_SPIMOSI0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
11
,
S3C2410_GPE11_SPIMISO0
);
s3c2410_gpio_pullup
(
S3C2410_GPE
11
,
0
);
s3c2410_gpio_pullup
(
S3C2410_GPE
13
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
13
)
,
S3C2410_GPE13_SPICLK0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
12
)
,
S3C2410_GPE12_SPIMOSI0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
11
)
,
S3C2410_GPE11_SPIMISO0
);
s3c2410_gpio_pullup
(
S3C2410_GPE
(
11
)
,
0
);
s3c2410_gpio_pullup
(
S3C2410_GPE
(
13
)
,
0
);
}
else
{
s3c2410_gpio_cfgpin
(
S3C2410_GPE
13
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
11
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPE
11
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPE
12
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPE
13
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
13
)
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE
(
11
)
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPE
(
11
)
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPE
(
12
)
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPE
(
13
)
,
1
);
}
}
arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c
View file @
99ae9953
...
...
@@ -22,16 +22,16 @@ void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
int
enable
)
{
if
(
enable
)
{
s3c2410_gpio_cfgpin
(
S3C2410_GPG
7
,
S3C2410_GPG7_SPICLK1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
6
,
S3C2410_GPG6_SPIMOSI1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
5
,
S3C2410_GPG5_SPIMISO1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
5
,
0
);
s3c2410_gpio_pullup
(
S3C2410_GPG
6
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
7
)
,
S3C2410_GPG7_SPICLK1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
6
)
,
S3C2410_GPG6_SPIMOSI1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
5
)
,
S3C2410_GPG5_SPIMISO1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
(
5
)
,
0
);
s3c2410_gpio_pullup
(
S3C2410_GPG
(
6
)
,
0
);
}
else
{
s3c2410_gpio_cfgpin
(
S3C2410_GPG
7
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
5
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPG
5
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
6
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
7
,
1
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
7
)
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_cfgpin
(
S3C2410_GPG
(
5
)
,
S3C2410_GPIO_INPUT
);
s3c2410_gpio_pullup
(
S3C2410_GPG
(
5
)
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
(
6
)
,
1
);
s3c2410_gpio_pullup
(
S3C2410_GPG
(
7
)
,
1
);
}
}
drivers/leds/leds-h1940.c
View file @
99ae9953
...
...
@@ -16,6 +16,8 @@
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
#include <mach/h1940-latch.h>
...
...
drivers/leds/leds-s3c24xx.c
View file @
99ae9953
...
...
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
...
...
drivers/mmc/host/s3cmci.c
View file @
99ae9953
...
...
@@ -17,6 +17,7 @@
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/cpufreq.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/io.h>
...
...
@@ -1121,7 +1122,7 @@ static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
case
MMC_POWER_OFF
:
default:
s3c2410_gpio_setpin
(
S3C2410_GPE5
,
0
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE5
,
S3C2410_GP
E5_OUTP
);
s3c2410_gpio_cfgpin
(
S3C2410_GPE5
,
S3C2410_GP
IO_OUTPUT
);
if
(
host
->
is2440
)
mci_con
|=
S3C2440_SDICON_SDRESET
;
...
...
drivers/spi/spi_s3c24xx_gpio.c
View file @
99ae9953
...
...
@@ -17,6 +17,7 @@
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
...
...
sound/soc/s3c24xx/s3c2412-i2s.c
View file @
99ae9953
...
...
@@ -20,6 +20,7 @@
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/io.h>
...
...
sound/soc/s3c24xx/s3c2443-ac97.c
View file @
99ae9953
...
...
@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/wait.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/clk.h>
#include <sound/core.h>
...
...
sound/soc/s3c24xx/s3c24xx-i2s.c
View file @
99ae9953
...
...
@@ -21,6 +21,8 @@
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
...
...
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