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Commit 9a2044fc authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v3.15/fixes-gpmc' of... 

Merge tag 'omap-for-v3.15/fixes-gpmc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Merge fixes from Tony Lindgren:

Mostly fixes for occasional memory corruption caused by bad
timings for smc911x LAN9220 (and potentially LAN9221) devices
that were noted on a cm-t3730 system. Also fix THUMB mode
for SMP, and mailbox related warnings when booted with device
tree.

* tag 'omap-for-v3.15/fixes-gpmc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: AM3517: Disable absent IPs inherited from OMAP3
  ARM: dts: OMAP2: Fix interrupts for OMAP2420 mailbox
  ARM: dts: OMAP5: Add mailbox dt node to fix boot warning
  ARM: OMAP5: Switch to THUMB mode if needed on secondary CPU
  ARM: dts: am437x-gp-evm: Do not reset gpio5
  ARM: dts: omap3-igep0020: use SMSC9221 timings
  ARM: dts: Fix GPMC timings for LAN9220
  ARM: dts: Fix GPMC Ethernet timings for omap cm-t sbc-t boards for device tree
  ARM: dts: Fix bad OTG muxing for cm-t boards
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 12e8e595 4c051603
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arch/arm/boot/dts/am3517.dtsi
View file @ 9a2044fc
...@@ -62,5 +62,21 @@ uart4: serial@4809e000 { ...@@ -62,5 +62,21 @@ uart4: serial@4809e000 {
}; };
}; };
&iva {
status = "disabled";
};
&mailbox {
status = "disabled";
};
&mmu_isp {
status = "disabled";
};
&smartreflex_mpu_iva {
status = "disabled";
};
/include/ "am35xx-clocks.dtsi" /include/ "am35xx-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
arch/arm/boot/dts/am437x-gp-evm.dts
View file @ 9a2044fc
...@@ -117,6 +117,11 @@ &gpio4 { ...@@ -117,6 +117,11 @@ &gpio4 {
status = "okay"; status = "okay";
}; };
&gpio5 {
status = "okay";
ti,no-reset-on-init;
};
&mmc1 { &mmc1 {
status = "okay"; status = "okay";
vmmc-supply = <&vmmcsd_fixed>; vmmc-supply = <&vmmcsd_fixed>;
......
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
View file @ 9a2044fc
...@@ -24,11 +24,10 @@ ethernet@gpmc { ...@@ -24,11 +24,10 @@ ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115"; compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>; bank-width = <2>;
gpmc,mux-add-data; gpmc,mux-add-data;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <186>; gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <186>; gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <12>; gpmc,adv-rd-off-ns = <18>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>; gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>; gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>; gpmc,oe-off-ns = <168>;
...@@ -36,12 +35,10 @@ ethernet@gpmc { ...@@ -36,12 +35,10 @@ ethernet@gpmc {
gpmc,we-off-ns = <168>; gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>; gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>; gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>; gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <6>; gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <12>; gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <18>; gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen; gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>; vddvario-supply = <&vddvario>;
......
arch/arm/boot/dts/omap2.dtsi
View file @ 9a2044fc
...@@ -71,13 +71,6 @@ hdq1w: 1w@480b2000 { ...@@ -71,13 +71,6 @@ hdq1w: 1w@480b2000 {
interrupts = <58>; interrupts = <58>;
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
};
intc: interrupt-controller@1 { intc: interrupt-controller@1 {
compatible = "ti,omap2-intc"; compatible = "ti,omap2-intc";
interrupt-controller; interrupt-controller;
......
arch/arm/boot/dts/omap2420.dtsi
View file @ 9a2044fc
...@@ -125,6 +125,14 @@ msdi1: mmc@4809c000 { ...@@ -125,6 +125,14 @@ msdi1: mmc@4809c000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
};
timer1: timer@48028000 { timer1: timer@48028000 {
compatible = "ti,omap2420-timer"; compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>; reg = <0x48028000 0x400>;
......
arch/arm/boot/dts/omap2430.dtsi
View file @ 9a2044fc
...@@ -216,6 +216,13 @@ mmc2: mmc@480b4000 { ...@@ -216,6 +216,13 @@ mmc2: mmc@480b4000 {
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
mailbox: mailbox@48094000 {
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,hwmods = "mailbox";
};
timer1: timer@49018000 { timer1: timer@49018000 {
compatible = "ti,omap2420-timer"; compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>; reg = <0x49018000 0x400>;
......
arch/arm/boot/dts/omap3-cm-t3x30.dtsi
View file @ 9a2044fc
...@@ -10,18 +10,6 @@ cpu@0 { ...@@ -10,18 +10,6 @@ cpu@0 {
cpu0-supply = <&vcc>; cpu0-supply = <&vcc>;
}; };
}; };
vddvario: regulator-vddvario {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
}; };
&omap3_pmx_core { &omap3_pmx_core {
...@@ -35,58 +23,34 @@ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_1 ...@@ -35,58 +23,34 @@ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_1
hsusb0_pins: pinmux_hsusb0_pins { hsusb0_pins: pinmux_hsusb0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */ OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data0.hsusb2_data0 */
OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */ OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data3 */
OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */ OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data4 */
OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */ OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data5 */
OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data6 */
OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
>; >;
}; };
}; };
#include "omap-gpmc-smsc911x.dtsi"
&gpmc { &gpmc {
ranges = <5 0 0x2c000000 0x01000000>; ranges = <5 0 0x2c000000 0x01000000>;
smsc1: ethernet@5,0 { smsc1: ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115"; compatible = "smsc,lan9221", "smsc,lan9115";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&smsc1_pins>; pinctrl-0 = <&smsc1_pins>;
interrupt-parent = <&gpio6>; interrupt-parent = <&gpio6>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
reg = <5 0 0xff>; reg = <5 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
}; };
}; };
......
arch/arm/boot/dts/omap3-igep.dtsi
View file @ 9a2044fc
...@@ -107,7 +107,7 @@ mmc2_pins: pinmux_mmc2_pins { ...@@ -107,7 +107,7 @@ mmc2_pins: pinmux_mmc2_pins {
>; >;
}; };
smsc911x_pins: pinmux_smsc911x_pins { smsc9221_pins: pinmux_smsc9221_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
>; >;
......
arch/arm/boot/dts/omap3-igep0020.dts
View file @ 9a2044fc
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
*/ */
#include "omap3-igep.dtsi" #include "omap3-igep.dtsi"
#include "omap-gpmc-smsc911x.dtsi" #include "omap-gpmc-smsc9221.dtsi"
/ { / {
model = "IGEPv2 (TI OMAP AM/DM37x)"; model = "IGEPv2 (TI OMAP AM/DM37x)";
...@@ -248,7 +248,7 @@ partition@780000 { ...@@ -248,7 +248,7 @@ partition@780000 {
ethernet@gpmc { ethernet@gpmc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&smsc911x_pins>; pinctrl-0 = <&smsc9221_pins>;
reg = <5 0 0xff>; reg = <5 0 0xff>;
interrupt-parent = <&gpio6>; interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
......
arch/arm/boot/dts/omap3-sb-t35.dtsi
View file @ 9a2044fc
...@@ -2,20 +2,6 @@ ...@@ -2,20 +2,6 @@
* Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
*/ */
/ {
vddvario_sb_t35: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&omap3_pmx_core { &omap3_pmx_core {
smsc2_pins: pinmux_smsc2_pins { smsc2_pins: pinmux_smsc2_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
...@@ -37,11 +23,10 @@ smsc2: ethernet@4,0 { ...@@ -37,11 +23,10 @@ smsc2: ethernet@4,0 {
reg = <4 0 0xff>; reg = <4 0 0xff>;
bank-width = <2>; bank-width = <2>;
gpmc,mux-add-data; gpmc,mux-add-data;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <1>;
gpmc,cs-rd-off-ns = <186>; gpmc,cs-rd-off-ns = <180>;
gpmc,cs-wr-off-ns = <186>; gpmc,cs-wr-off-ns = <180>;
gpmc,adv-on-ns = <12>; gpmc,adv-rd-off-ns = <18>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>; gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>; gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>; gpmc,oe-off-ns = <168>;
...@@ -49,16 +34,14 @@ smsc2: ethernet@4,0 { ...@@ -49,16 +34,14 @@ smsc2: ethernet@4,0 {
gpmc,we-off-ns = <168>; gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>; gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>; gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>; gpmc,access-ns = <144>;
gpmc,page-burst-access-ns = <6>; gpmc,page-burst-access-ns = <24>;
gpmc,bus-turnaround-ns = <12>; gpmc,bus-turnaround-ns = <90>;
gpmc,cycle2cycle-delay-ns = <18>; gpmc,cycle2cycle-delay-ns = <90>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen; gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen; gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario_sb_t35>; vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a_sb_t35>; vdd33a-supply = <&vdd33a>;
reg-io-width = <4>; reg-io-width = <4>;
smsc,save-mac-address; smsc,save-mac-address;
}; };
......
arch/arm/boot/dts/omap3-sbc-t3517.dts
View file @ 9a2044fc
...@@ -8,6 +8,19 @@ ...@@ -8,6 +8,19 @@
/ { / {
model = "CompuLab SBC-T3517 with CM-T3517"; model = "CompuLab SBC-T3517 with CM-T3517";
compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
/* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
vddvario: regulator-vddvario-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a-sb-t35 {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
}; };
&omap3_pmx_core { &omap3_pmx_core {
......
arch/arm/boot/dts/omap3.dtsi
View file @ 9a2044fc
...@@ -61,7 +61,7 @@ mpu { ...@@ -61,7 +61,7 @@ mpu {
ti,hwmods = "mpu"; ti,hwmods = "mpu";
}; };
iva { iva: iva {
compatible = "ti,iva2.2"; compatible = "ti,iva2.2";
ti,hwmods = "iva"; ti,hwmods = "iva";
......
arch/arm/boot/dts/omap5.dtsi
View file @ 9a2044fc
...@@ -630,6 +630,13 @@ mcbsp3: mcbsp@40126000 { ...@@ -630,6 +630,13 @@ mcbsp3: mcbsp@40126000 {
status = "disabled"; status = "disabled";
}; };
mailbox: mailbox@4a0f4000 {
compatible = "ti,omap4-mailbox";
reg = <0x4a0f4000 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mailbox";
};
timer1: timer@4ae18000 { timer1: timer@4ae18000 {
compatible = "ti,omap5430-timer"; compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>; reg = <0x4ae18000 0x80>;
......
arch/arm/mach-omap2/omap-headsmp.S
View file @ 9a2044fc
/* /*
* Secondary CPU startup routine source file. * Secondary CPU startup routine source file.
* *
* Copyright (C) 2009 Texas Instruments, Inc. * Copyright (C) 2009-2014 Texas Instruments, Inc.
* *
* Author: * Author:
* Santosh Shilimkar <santosh.shilimkar@ti.com> * Santosh Shilimkar <santosh.shilimkar@ti.com>
...@@ -28,9 +28,13 @@ ...@@ -28,9 +28,13 @@
* code. This routine also provides a holding flag into which * code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise. * secondary core is held until we're ready for it to initialise.
* The primary core will update this flag using a hardware * The primary core will update this flag using a hardware
+ * register AuxCoreBoot0. * register AuxCoreBoot0.
*/ */
ENTRY(omap5_secondary_startup) ENTRY(omap5_secondary_startup)
.arm
THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
ldr r0, [r2] ldr r0, [r2]
mov r0, r0, lsr #5 mov r0, r0, lsr #5
......
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