drm/i915/guc/ct: Stop expecting multiple CT channels

The GuC supports having multiple CT buffer pairs and we designed our
implementation with that in mind. However, the different channels are not
processed in parallel within the GuC, so there is very little advantage
in having multiple channels (independent locks?), compared to the
drawbacks (one channel can starve the other if messages keep being
submitted to it). Given this, it is unlikely we'll ever add a second
channel and therefore we can simplify our code by removing the
flexibility.

v2: split substructure grouping to separate patch, improve docs (Michal)
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191217012316.13271-3-daniele.ceraolospurio@intel.com
parent 7f5390c4
This diff is collapsed.
...@@ -35,44 +35,25 @@ struct intel_guc_ct_buffer { ...@@ -35,44 +35,25 @@ struct intel_guc_ct_buffer {
u32 *cmds; u32 *cmds;
}; };
/** Represents pair of command transport buffers.
*
* Buffers go in pairs to allow bi-directional communication.
* To simplify the code we place both of them in the same vma.
* Buffers from the same pair must share unique owner id.
*
* @vma: pointer to the vma with pair of CT buffers
* @ctbs: buffers for sending(0) and receiving(1) commands
* @owner: unique identifier
* @next_fence: fence to be used with next send command
*/
struct intel_guc_ct_channel {
struct i915_vma *vma;
struct intel_guc_ct_buffer ctbs[2];
u32 owner;
u32 next_fence;
bool enabled;
};
/** Holds all command transport channels. /** Top-level structure for Command Transport related data
* *
* @host_channel: main channel used by the host * Includes a pair of CT buffers for bi-directional communication and tracking
* for the H2G and G2H requests sent and received through the buffers.
*/ */
struct intel_guc_ct { struct intel_guc_ct {
struct intel_guc_ct_channel host_channel; struct i915_vma *vma;
/* other channels are tbd */ bool enabled;
/** @lock: protects pending requests list */
spinlock_t lock;
/** @pending_requests: list of requests waiting for response */ /* buffers for sending(0) and receiving(1) commands */
struct list_head pending_requests; struct intel_guc_ct_buffer ctbs[2];
/** @incoming_requests: list of incoming requests */ u32 next_fence; /* fence to be used with next send command */
struct list_head incoming_requests;
/** @worker: worker for handling incoming requests */ spinlock_t lock; /* protects pending requests list */
struct work_struct worker; struct list_head pending_requests; /* requests waiting for response */
struct list_head incoming_requests; /* incoming requests */
struct work_struct worker; /* handler for incoming requests */
}; };
void intel_guc_ct_init_early(struct intel_guc_ct *ct); void intel_guc_ct_init_early(struct intel_guc_ct *ct);
......
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