[TIGON3]: Merge to version 1.1

- When not low-power, only set GPIO enables in lclctrl on
5700 chips
- Follow all writes to foo DMAC_MODE with a readback and
udelay(40)
- Be explicit about the fact that the driver disables wake-on-lan
by default and how the user may enable it
- A few NIC_SRAM_DATA_CFG_foo bits were wrong or missing
- Clock control programming for some chips when going to low
power mode was wrong.
- Bump driver version/reldata for release
- PCI write posting fixes
  * Sanitize every PCI write that requires a delay afterwards by
    doing a dummy read back from the register.
  * Handle the interesting case of this when doing a core-clock
    reset by using PCI config space indirect writes to GRC_MISC_CFG
    since we cannot do an MMIO read back from the chip during this
    reset event because it clears MMIO space enable in PCI_CONFIG
  * Add a new tg3_flag TG3_FLAG_MBOX_WRITE_REORDER which is set
    on chipsets that may violate PCI write ordering rules, when
    set we always read back from tx/rx ring mailbox registers after
    a write to guarentee the writes appear to the chip in order.
- Make sure to always enable AS_MASTER bits when necessary
- PHY reset fixes
  * Always reset PHY on init, for every chip revision
  * Program 5703 specific PHY stuff after the reset
  * Always enable Ethernet@WireSpeed after that reset
  * Always set ADVERTISE_PAUSE_CAP in initial adv reg.

drivers/net/tg3.h

@@ -1248,14 +1248,19 @@
 #define  NIC_SRAM_DATA_SIG_MAGIC	 0x4b657654 /* ascii for 'KevT' */
 
 #define NIC_SRAM_DATA_CFG			0x00000b58
-#define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK	 0x0000000c
-#define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN	 0x00000000
-#define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER	 0x00000004
-#define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER	 0x00000008
-#define  NIC_SRAM_DATA_CFG_LED_MODE_MASK	 0x00000030
+#define  NIC_SRAM_DATA_CFG_LED_MODE_MASK	 0x0000000c
 #define  NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN	 0x00000000
-#define  NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD	 0x00000010
-#define  NIC_SRAM_DATA_CFG_LED_LINK_SPD		 0x00000020
+#define  NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD	 0x00000004
+#define  NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN	 0x00000004
+#define  NIC_SRAM_DATA_CFG_LED_LINK_SPD		 0x00000008
+#define  NIC_SRAM_DATA_CFG_LED_OUTPUT		 0x00000008
+#define  NIC_SRAM_DATA_CFG_PHY_TYPE_MASK	 0x00000030
+#define  NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN	 0x00000000
+#define  NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER	 0x00000010
+#define  NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER	 0x00000020
+#define  NIC_SRAM_DATA_CFG_WOL_ENABLE		 0x00000040
+#define  NIC_SRAM_DATA_CFG_ASF_ENABLE		 0x00000080
+#define  NIC_SRAM_DATA_CFG_EEPROM_WP		 0x00000100
 
 #define NIC_SRAM_DATA_PHY_ID		0x00000b74
 #define  NIC_SRAM_DATA_PHY_ID1_MASK	 0xffff0000
@@ -1738,10 +1743,11 @@ struct tg3 {
 #define TG3_FLAG_USE_LINKCHG_REG	0x00000008
 #define TG3_FLAG_USE_MI_INTERRUPT	0x00000010
 #define TG3_FLAG_POLL_SERDES		0x00000080
-#define TG3_FLAG_PHY_RESET_ON_INIT	0x00000100
+#define TG3_FLAG_MBOX_WRITE_REORDER	0x00000100
 #define TG3_FLAG_PCIX_TARGET_HWBUG	0x00000200
 #define TG3_FLAG_WOL_SPEED_100MB	0x00000400
-#define TG3_FLAG_WOL_ENABLE		0x00001000
+#define TG3_FLAG_WOL_ENABLE		0x00000800
+#define TG3_FLAG_EEPROM_WRITE_PROT	0x00001000
 #define TG3_FLAG_NVRAM			0x00002000
 #define TG3_FLAG_NVRAM_BUFFERED		0x00004000
 #define TG3_FLAG_RX_PAUSE		0x00008000