Commit 9d61707b authored by Jim Lin's avatar Jim Lin Committed by Mike Turquette

clk: tegra: Fix xusb_fs_src mux

The parent-to-index mapping for xusb_fs_src is incorrect.
Fix it by adding a mux table.
Signed-off-by: default avatarJim Lin <jilin@nvidia.com>
Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent 2cfe1674
...@@ -329,7 +329,9 @@ static u32 mux_clkm_pllp_pllc_pllre_idx[] = { ...@@ -329,7 +329,9 @@ static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
static const char *mux_clkm_48M_pllp_480M[] = { static const char *mux_clkm_48M_pllp_480M[] = {
"clk_m", "pll_u_48M", "pll_p", "pll_u_480M" "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
}; };
#define mux_clkm_48M_pllp_480M_idx NULL static u32 mux_clkm_48M_pllp_480M_idx[] = {
[0] = 0, [1] = 2, [2] = 4, [3] = 6,
};
static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
"clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
......
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