Commit 9df11828 authored by Florian Fainelli's avatar Florian Fainelli

ARM: dts: BCM63xx: fix L2 cache properties

The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.

Fixes: 46d4bca0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent 97bf6af1
...@@ -66,8 +66,9 @@ L2: cache-controller@1d000 { ...@@ -66,8 +66,9 @@ L2: cache-controller@1d000 {
reg = <0x1d000 0x1000>; reg = <0x1d000 0x1000>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
cache-sets = <16>; cache-size = <524288>;
cache-size = <0x80000>; cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
}; };
......
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