Commit a10a1f60 authored by Bjorn Helgaas's avatar Bjorn Helgaas

Merge branch 'pci/enumeration'

  - Consolidate _HPP & _HPX code in pci-acpi.h and remove unnecessary
    struct hotplug_program_ops (Krzysztof Wilczynski)

  - Fixup PCIe device types to remove the need for dev->has_secondary_link
    (Mika Westerberg)

* pci/enumeration:
  PCI: Get rid of dev->has_secondary_link flag
  PCI: Make pcie_downstream_port() available outside of access.c
  PCI/ACPI: Remove unnecessary struct hotplug_program_ops
  PCI/ACPI: Move _HPP & _HPX functions to pci-acpi.c
  PCI/ACPI: Rename _HPX structs from hpp_* to hpx_*
parents 77dc51fd ca784104
...@@ -336,15 +336,6 @@ static inline int pcie_cap_version(const struct pci_dev *dev) ...@@ -336,15 +336,6 @@ static inline int pcie_cap_version(const struct pci_dev *dev)
return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS; return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
} }
static bool pcie_downstream_port(const struct pci_dev *dev)
{
int type = pci_pcie_type(dev);
return type == PCI_EXP_TYPE_ROOT_PORT ||
type == PCI_EXP_TYPE_DOWNSTREAM ||
type == PCI_EXP_TYPE_PCIE_BRIDGE;
}
bool pcie_cap_has_lnkctl(const struct pci_dev *dev) bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
{ {
int type = pci_pcie_type(dev); int type = pci_pcie_type(dev);
......
This diff is collapsed.
...@@ -3576,7 +3576,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) ...@@ -3576,7 +3576,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
} }
/* Ensure upstream ports don't block AtomicOps on egress */ /* Ensure upstream ports don't block AtomicOps on egress */
if (!bridge->has_secondary_link) { if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
&ctl2); &ctl2);
if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK) if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
......
...@@ -125,6 +125,15 @@ static inline bool pci_power_manageable(struct pci_dev *pci_dev) ...@@ -125,6 +125,15 @@ static inline bool pci_power_manageable(struct pci_dev *pci_dev)
return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
} }
static inline bool pcie_downstream_port(const struct pci_dev *dev)
{
int type = pci_pcie_type(dev);
return type == PCI_EXP_TYPE_ROOT_PORT ||
type == PCI_EXP_TYPE_DOWNSTREAM ||
type == PCI_EXP_TYPE_PCIE_BRIDGE;
}
int pci_vpd_init(struct pci_dev *dev); int pci_vpd_init(struct pci_dev *dev);
void pci_vpd_release(struct pci_dev *dev); void pci_vpd_release(struct pci_dev *dev);
void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev); void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
...@@ -650,4 +659,13 @@ static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } ...@@ -650,4 +659,13 @@ static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
static inline void pci_aer_clear_device_status(struct pci_dev *dev) { } static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
#endif #endif
#ifdef CONFIG_ACPI
int pci_acpi_program_hp_params(struct pci_dev *dev);
#else
static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
{
return -ENODEV;
}
#endif
#endif /* DRIVERS_PCI_H */ #endif /* DRIVERS_PCI_H */
...@@ -912,10 +912,10 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev) ...@@ -912,10 +912,10 @@ void pcie_aspm_init_link_state(struct pci_dev *pdev)
/* /*
* We allocate pcie_link_state for the component on the upstream * We allocate pcie_link_state for the component on the upstream
* end of a Link, so there's nothing to do unless this device has a * end of a Link, so there's nothing to do unless this device is
* Link on its secondary side. * downstream port.
*/ */
if (!pdev->has_secondary_link) if (!pcie_downstream_port(pdev))
return; return;
/* VIA has a strange chipset, root port is under a bridge */ /* VIA has a strange chipset, root port is under a bridge */
...@@ -1069,7 +1069,7 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem) ...@@ -1069,7 +1069,7 @@ static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
if (!pci_is_pcie(pdev)) if (!pci_is_pcie(pdev))
return 0; return 0;
if (pdev->has_secondary_link) if (pcie_downstream_port(pdev))
parent = pdev; parent = pdev;
if (!parent || !parent->link_state) if (!parent || !parent->link_state)
return -EINVAL; return -EINVAL;
......
...@@ -166,7 +166,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service) ...@@ -166,7 +166,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service)
driver = pcie_port_find_service(dev, service); driver = pcie_port_find_service(dev, service);
if (driver && driver->reset_link) { if (driver && driver->reset_link) {
status = driver->reset_link(dev); status = driver->reset_link(dev);
} else if (dev->has_secondary_link) { } else if (pcie_downstream_port(dev)) {
status = default_reset_link(dev); status = default_reset_link(dev);
} else { } else {
pci_printk(KERN_DEBUG, dev, "no link-reset support at upstream device %s\n", pci_printk(KERN_DEBUG, dev, "no link-reset support at upstream device %s\n",
......
This diff is collapsed.
...@@ -13,6 +13,8 @@ ...@@ -13,6 +13,8 @@
#include <linux/pci_regs.h> #include <linux/pci_regs.h>
#include <linux/types.h> #include <linux/types.h>
#include "pci.h"
/** /**
* pci_vc_save_restore_dwords - Save or restore a series of dwords * pci_vc_save_restore_dwords - Save or restore a series of dwords
* @dev: device * @dev: device
...@@ -105,7 +107,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res) ...@@ -105,7 +107,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
struct pci_dev *link = NULL; struct pci_dev *link = NULL;
/* Enable VCs from the downstream device */ /* Enable VCs from the downstream device */
if (!dev->has_secondary_link) if (!pci_is_pcie(dev) || !pcie_downstream_port(dev))
return; return;
ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF); ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
......
...@@ -419,7 +419,6 @@ struct pci_dev { ...@@ -419,7 +419,6 @@ struct pci_dev {
unsigned int broken_intx_masking:1; /* INTx masking can't be used */ unsigned int broken_intx_masking:1; /* INTx masking can't be used */
unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
unsigned int irq_managed:1; unsigned int irq_managed:1;
unsigned int has_secondary_link:1;
unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
unsigned int is_probed:1; /* Device probing in progress */ unsigned int is_probed:1; /* Device probing in progress */
unsigned int link_active_reporting:1;/* Device capable of reporting link active */ unsigned int link_active_reporting:1;/* Device capable of reporting link active */
......
...@@ -86,114 +86,14 @@ void pci_hp_deregister(struct hotplug_slot *slot); ...@@ -86,114 +86,14 @@ void pci_hp_deregister(struct hotplug_slot *slot);
#define pci_hp_initialize(slot, bus, nr, name) \ #define pci_hp_initialize(slot, bus, nr, name) \
__pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME) __pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME)
/* PCI Setting Record (Type 0) */
struct hpp_type0 {
u32 revision;
u8 cache_line_size;
u8 latency_timer;
u8 enable_serr;
u8 enable_perr;
};
/* PCI-X Setting Record (Type 1) */
struct hpp_type1 {
u32 revision;
u8 max_mem_read;
u8 avg_max_split;
u16 tot_max_split;
};
/* PCI Express Setting Record (Type 2) */
struct hpp_type2 {
u32 revision;
u32 unc_err_mask_and;
u32 unc_err_mask_or;
u32 unc_err_sever_and;
u32 unc_err_sever_or;
u32 cor_err_mask_and;
u32 cor_err_mask_or;
u32 adv_err_cap_and;
u32 adv_err_cap_or;
u16 pci_exp_devctl_and;
u16 pci_exp_devctl_or;
u16 pci_exp_lnkctl_and;
u16 pci_exp_lnkctl_or;
u32 sec_unc_err_sever_and;
u32 sec_unc_err_sever_or;
u32 sec_unc_err_mask_and;
u32 sec_unc_err_mask_or;
};
/*
* _HPX PCI Express Setting Record (Type 3)
*/
struct hpx_type3 {
u16 device_type;
u16 function_type;
u16 config_space_location;
u16 pci_exp_cap_id;
u16 pci_exp_cap_ver;
u16 pci_exp_vendor_id;
u16 dvsec_id;
u16 dvsec_rev;
u16 match_offset;
u32 match_mask_and;
u32 match_value;
u16 reg_offset;
u32 reg_mask_and;
u32 reg_mask_or;
};
struct hotplug_program_ops {
void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp);
void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp);
void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp);
void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp);
};
enum hpx_type3_dev_type {
HPX_TYPE_ENDPOINT = BIT(0),
HPX_TYPE_LEG_END = BIT(1),
HPX_TYPE_RC_END = BIT(2),
HPX_TYPE_RC_EC = BIT(3),
HPX_TYPE_ROOT_PORT = BIT(4),
HPX_TYPE_UPSTREAM = BIT(5),
HPX_TYPE_DOWNSTREAM = BIT(6),
HPX_TYPE_PCI_BRIDGE = BIT(7),
HPX_TYPE_PCIE_BRIDGE = BIT(8),
};
enum hpx_type3_fn_type {
HPX_FN_NORMAL = BIT(0),
HPX_FN_SRIOV_PHYS = BIT(1),
HPX_FN_SRIOV_VIRT = BIT(2),
};
enum hpx_type3_cfg_loc {
HPX_CFG_PCICFG = 0,
HPX_CFG_PCIE_CAP = 1,
HPX_CFG_PCIE_CAP_EXT = 2,
HPX_CFG_VEND_CAP = 3,
HPX_CFG_DVSEC = 4,
HPX_CFG_MAX,
};
#ifdef CONFIG_ACPI #ifdef CONFIG_ACPI
#include <linux/acpi.h> #include <linux/acpi.h>
int pci_acpi_program_hp_params(struct pci_dev *dev,
const struct hotplug_program_ops *hp_ops);
bool pciehp_is_native(struct pci_dev *bridge); bool pciehp_is_native(struct pci_dev *bridge);
int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge); int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge);
bool shpchp_is_native(struct pci_dev *bridge); bool shpchp_is_native(struct pci_dev *bridge);
int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle); int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle);
int acpi_pci_detect_ejectable(acpi_handle handle); int acpi_pci_detect_ejectable(acpi_handle handle);
#else #else
static inline int pci_acpi_program_hp_params(struct pci_dev *dev,
const struct hotplug_program_ops *hp_ops)
{
return -ENODEV;
}
static inline int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge) static inline int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge)
{ {
return 0; return 0;
......
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