Commit a20aea39 authored by Alex Deucher's avatar Alex Deucher Committed by Jiri Slaby

drm/radeon/si_dpm: workaround for SI kickers

commit 7dc86ef5 upstream.

Consolidate existing quirks. Fixes stability issues
on some kickers.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarJiri Slaby <jslaby@suse.cz>
parent 396e52fe
......@@ -2934,6 +2934,49 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
int i;
struct si_dpm_quirk *p = si_dpm_quirk_list;
/* limit all SI kickers */
if (rdev->family == CHIP_PITCAIRN) {
if ((rdev->pdev->revision == 0x81) ||
(rdev->pdev->device == 0x6810) ||
(rdev->pdev->device == 0x6811) ||
(rdev->pdev->device == 0x6816) ||
(rdev->pdev->device == 0x6817) ||
(rdev->pdev->device == 0x6806))
max_mclk = 120000;
} else if (rdev->family == CHIP_VERDE) {
if ((rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->revision == 0x87) ||
(rdev->pdev->device == 0x6820) ||
(rdev->pdev->device == 0x6821) ||
(rdev->pdev->device == 0x6822) ||
(rdev->pdev->device == 0x6823) ||
(rdev->pdev->device == 0x682A) ||
(rdev->pdev->device == 0x682B)) {
max_sclk = 75000;
max_mclk = 80000;
}
} else if (rdev->family == CHIP_OLAND) {
if ((rdev->pdev->revision == 0xC7) ||
(rdev->pdev->revision == 0x80) ||
(rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->device == 0x6604) ||
(rdev->pdev->device == 0x6605)) {
max_sclk = 75000;
max_mclk = 80000;
}
} else if (rdev->family == CHIP_HAINAN) {
if ((rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->revision == 0xC3) ||
(rdev->pdev->device == 0x6664) ||
(rdev->pdev->device == 0x6665) ||
(rdev->pdev->device == 0x6667)) {
max_sclk = 75000;
max_mclk = 80000;
}
}
/* Apply dpm quirks */
while (p && p->chip_device != 0) {
if (rdev->pdev->vendor == p->chip_vendor &&
......@@ -3008,22 +3051,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
ps->performance_levels[i].sclk = max_sclk;
}
}
/* limit mclk on all R7 370 parts for stability */
if (rdev->pdev->device == 0x6811 &&
rdev->pdev->revision == 0x81)
max_mclk = 120000;
/* limit sclk/mclk on Jet parts for stability */
if (rdev->pdev->device == 0x6665 &&
rdev->pdev->revision == 0xc3) {
max_sclk = 75000;
max_mclk = 80000;
}
/* limit clocks on HD8600 series */
if (rdev->pdev->device == 0x6660 &&
rdev->pdev->revision == 0x83) {
max_sclk = 75000;
max_mclk = 80000;
}
/* XXX validate the min clocks required for display */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment