[ARM PATCH] 1847/1: OMAP update 2/2: include files

Patch from Tony Lindgren

This patch syncs the mainline kernel with the linux-omap tree. The
patch contains following updates:
- Move virtual IO area to 0xfefb0000 from 0xfffb0000 to fix parts of
  IO area  overlapping with ARM Linux reserved memory area
- Add support to OMAP-730, OMAP-5912, and OMAP-1710 processors
- Reorganize board support
- Add OMAP core detection
This patch requires ARM Linux patch 1844/1 be applied to compile
OMAP-730 and OMAP-5912

include/asm-arm/arch-omap/board-h2.h

+/*
+ * linux/include/asm-arm/arch-omap/board-h2.h
+ *
+ * Hardware definitions for TI OMAP1610 H2 board.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H2_H
+#define __ASM_ARCH_OMAP_H2_H
+
+/* Placeholder for H2 specific defines */
+
+#endif /*  __ASM_ARCH_OMAP_H2_H */
+

include/asm-arm/arch-omap/board-h3.h

+/*
+ * linux/include/asm-arm/arch-omap/board-h3.h
+ *
+ * Hardware definitions for TI OMAP1610 H3 board.
+ *
+ * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H3_H
+#define __ASM_ARCH_OMAP_H3_H
+
+/* Placeholder for H3 specific defines */
+
+#endif /*  __ASM_ARCH_OMAP_H3_H */
+

include/asm-arm/arch-omap/board-h4.h

+/*
+ * linux/include/asm-arm/arch-omap/board-h4.h
+ *
+ * Hardware definitions for TI OMAP1610 H4 board.
+ *
+ * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H4_H
+#define __ASM_ARCH_OMAP_H4_H
+
+/* Placeholder for H4 specific defines */
+
+#endif /*  __ASM_ARCH_OMAP_H4_H */
+

include/asm-arm/arch-omap/board-innovator.h

+/*
+ * linux/include/asm-arm/arch-omap/board-innovator.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
+#define __ASM_ARCH_OMAP_INNOVATOR_H
+
+#if defined (CONFIG_ARCH_OMAP1510)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510P1_FPGA_BASE			0xE8000000	/* Virtual */
+#define OMAP1510P1_FPGA_SIZE			SZ_4K
+#define OMAP1510P1_FPGA_START			0x08000000	/* Physical */
+
+/* Revision */
+#define OMAP1510P1_FPGA_REV_LOW			(OMAP1510P1_FPGA_BASE + 0x0)
+#define OMAP1510P1_FPGA_REV_HIGH		(OMAP1510P1_FPGA_BASE + 0x1)
+
+#define OMAP1510P1_FPGA_LCD_PANEL_CONTROL	(OMAP1510P1_FPGA_BASE + 0x2)
+#define OMAP1510P1_FPGA_LED_DIGIT		(OMAP1510P1_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI			(OMAP1510P1_FPGA_BASE + 0x4)
+#define OMAP1510P1_FPGA_POWER			(OMAP1510P1_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510P1_FPGA_ISR_LO			(OMAP1510P1_FPGA_BASE + 0x6)
+#define OMAP1510P1_FPGA_ISR_HI			(OMAP1510P1_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510P1_FPGA_IMR_LO			(OMAP1510P1_FPGA_BASE + 0x8)
+#define OMAP1510P1_FPGA_IMR_HI			(OMAP1510P1_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510P1_FPGA_HOST_RESET		(OMAP1510P1_FPGA_BASE + 0xa)
+#define OMAP1510P1_FPGA_RST			(OMAP1510P1_FPGA_BASE + 0xb)
+
+#define OMAP1510P1_FPGA_AUDIO			(OMAP1510P1_FPGA_BASE + 0xc)
+#define OMAP1510P1_FPGA_DIP			(OMAP1510P1_FPGA_BASE + 0xe)
+#define OMAP1510P1_FPGA_FPGA_IO			(OMAP1510P1_FPGA_BASE + 0xf)
+#define OMAP1510P1_FPGA_UART1			(OMAP1510P1_FPGA_BASE + 0x14)
+#define OMAP1510P1_FPGA_UART2			(OMAP1510P1_FPGA_BASE + 0x15)
+#define OMAP1510P1_FPGA_OMAP1510_STATUS		(OMAP1510P1_FPGA_BASE + 0x16)
+#define OMAP1510P1_FPGA_BOARD_REV		(OMAP1510P1_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA			(OMAP1510P1_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS			(OMAP1510P1_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL			(OMAP1510P1_FPGA_BASE + 0x102)
+
+#define OMAP1510P1_FPGA_TOUCHSCREEN		(OMAP1510P1_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO			(OMAP1510P1_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO		(OMAP1510P1_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI		(OMAP1510P1_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO		(OMAP1510P1_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI		(OMAP1510P1_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO		(OMAP1510P1_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI		(OMAP1510P1_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL		(OMAP1510P1_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL		(OMAP1510P1_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2			(OMAP1510P1_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2			(OMAP1510P1_FPGA_BASE + 0x210)
+
+#define OMAP1510P1_FPGA_ETHR_START		(OMAP1510P1_FPGA_START + 0x300)
+#define OMAP1510P1_FPGA_ETHR_BASE		(OMAP1510P1_FPGA_BASE + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510P1_FPGA_RESET_VALUE		0x42
+
+#define OMAP1510P1_FPGA_PCR_IF_PD0		(1 << 7)
+#define OMAP1510P1_FPGA_PCR_COM2_EN		(1 << 6)
+#define OMAP1510P1_FPGA_PCR_COM1_EN		(1 << 5)
+#define OMAP1510P1_FPGA_PCR_EXP_PD0		(1 << 4)
+#define OMAP1510P1_FPGA_PCR_EXP_PD1		(1 << 3)
+#define OMAP1510P1_FPGA_PCR_48MHZ_CLK		(1 << 2)
+#define OMAP1510P1_FPGA_PCR_4MHZ_CLK		(1 << 1)
+#define OMAP1510P1_FPGA_PCR_RSRVD_BIT0		(1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define FPGA_HID_SCLK	(1<<0)	/* output */
+#define FPGA_HID_MOSI	(1<<1)	/* output */
+#define FPGA_HID_nSS	(1<<2)	/* output 0/1 chip idle/select */
+#define FPGA_HID_nHSUS	(1<<3)	/* output 0/1 host active/suspended */
+#define FPGA_HID_MISO	(1<<4)	/* input */
+#define FPGA_HID_ATN	(1<<5)	/* input  0/1 chip idle/ATN */
+#define FPGA_HID_rsrvd	(1<<6)
+#define FPGA_HID_RESETn (1<<7)	/* output - 0/1 USAR reset/run */
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE			D256M_1X16_4B
+#endif
+
+#define OMAP1510P1_IMIF_PRI_VALUE		0x00
+#define OMAP1510P1_EMIFS_PRI_VALUE		0x00
+#define OMAP1510P1_EMIFF_PRI_VALUE		0x00
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option. The flash address used here must
+ * fall within the legal range defined by rrload for storing
+ * the filesystem component. This address will be sufficiently
+ * deep into the overall flash range to avoid the other
+ * components also stored in flash such as the bootloader,
+ * the bootloader params, and the kernel.
+ * The SW2 settings for the map below are:
+ * 1 off, 2 off, 3 on, 4 off.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE	0xD8000000
+#define OMAP_FLASH_0_START	0x00000000
+#define OMAP_FLASH_0_SIZE	SZ_16M
+
+/* Intel flash_1, used for cramfs or other flash file systems */
+#define OMAP_FLASH_1_BASE	0xD9000000
+#define OMAP_FLASH_1_START	0x01000000
+#define OMAP_FLASH_1_SIZE	SZ_16M
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define INT_FPGA		(IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define IH_FPGA_BASE		IH_BOARD_BASE
+#define INT_FPGA_ATN		(IH_FPGA_BASE + 0)
+#define INT_FPGA_ACK		(IH_FPGA_BASE + 1)
+#define INT_FPGA2		(IH_FPGA_BASE + 2)
+#define INT_FPGA3		(IH_FPGA_BASE + 3)
+#define INT_FPGA4		(IH_FPGA_BASE + 4)
+#define INT_FPGA5		(IH_FPGA_BASE + 5)
+#define INT_FPGA6		(IH_FPGA_BASE + 6)
+#define INT_FPGA7		(IH_FPGA_BASE + 7)
+#define INT_FPGA8		(IH_FPGA_BASE + 8)
+#define INT_FPGA9		(IH_FPGA_BASE + 9)
+#define INT_FPGA10		(IH_FPGA_BASE + 10)
+#define INT_FPGA11		(IH_FPGA_BASE + 11)
+#define INT_FPGA12		(IH_FPGA_BASE + 12)
+#define INT_ETHER		(IH_FPGA_BASE + 13)
+#define INT_FPGAUART1		(IH_FPGA_BASE + 14)
+#define INT_FPGAUART2		(IH_FPGA_BASE + 15)
+#define INT_FPGA_TS		(IH_FPGA_BASE + 16)
+#define INT_FPGA17		(IH_FPGA_BASE + 17)
+#define INT_FPGA_CAM		(IH_FPGA_BASE + 18)
+#define INT_FPGA_RTC_A		(IH_FPGA_BASE + 19)
+#define INT_FPGA_RTC_B		(IH_FPGA_BASE + 20)
+#define INT_FPGA_CD		(IH_FPGA_BASE + 21)
+#define INT_FPGA22		(IH_FPGA_BASE + 22)
+#define INT_FPGA23		(IH_FPGA_BASE + 23)
+
+#define NR_FPGA_IRQS		 24
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+#endif /* CONFIG_ARCH_OMAP1510 */
+
+#if defined (CONFIG_ARCH_OMAP1610)
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_BASE		0xE8000000
+#define OMAP1610_ETHR_SIZE		SZ_4K
+#define OMAP1610_ETHR_START		0x04000000
+
+/* Intel STRATA NOR flash at CS3 */
+#define OMAP1610_NOR_FLASH_BASE		0xD8000000
+#define OMAP1610_NOR_FLASH_SIZE		SZ_32M
+#define OMAP1610_NOR_FLASH_START	0x0C000000
+
+#endif /* CONFIG_ARCH_OMAP1610 */
+#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */

include/asm-arm/arch-omap/board-osk.h

+/*
+ * linux/include/asm-arm/arch-omap/board-osk.h
+ *
+ * Hardware definitions for TI OMAP5912 OSK board.
+ *
+ * Written by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_OSK_H
+#define __ASM_ARCH_OMAP_OSK_H
+
+/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
+#define OMAP_OSK_ETHR_BASE		0xE8800000
+#define OMAP_OSK_ETHR_SIZE		SZ_4K
+#define OMAP_OSK_ETHR_START		0x04800000
+
+/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
+#define OMAP_OSK_NOR_FLASH_BASE		0xD8000000
+#define OMAP_OSK_NOR_FLASH_SIZE		SZ_32M
+#define OMAP_OSK_NOR_FLASH_START	0x00000000
+
+#endif /*  __ASM_ARCH_OMAP_OSK_H */
+

include/asm-arm/arch-omap/board-perseus2.h

+/*
+ *  linux/include/asm-arm/arch-omap/board-perseus2.h
+ *
+ *  Copyright 2003 by Texas Instruments Incorporated
+ *    OMAP730 / P2-sample additions
+ *    Author: Jean Pihet
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_P2SAMPLE_H
+#define __ASM_ARCH_OMAP_P2SAMPLE_H
+
+#if defined(CONFIG_ARCH_OMAP730) && defined (CONFIG_MACH_OMAP_PERSEUS2)
+
+/*
+ * NOTE:  ALL DEFINITIONS IN THIS FILE NEED TO BE PREFIXED BY IDENTIFIER
+ *	  P2SAMPLE_ since they are specific to the EVM and not the chip.
+ */
+
+/* ---------------------------------------------------------------------------
+ *  OMAP730 Debug Board FPGA
+ * ---------------------------------------------------------------------------
+ */
+
+/* maps in the FPGA registers and the ETHR registers */
+#define OMAP730_FPGA_BASE		0xE8000000	/* VA */
+#define OMAP730_FPGA_SIZE		SZ_4K		/* SIZE */
+#define OMAP730_FPGA_START		0x04000000	/* PA */
+
+#define OMAP730_FPGA_ETHR_START		OMAP730_FPGA_START
+#define OMAP730_FPGA_ETHR_BASE		OMAP730_FPGA_BASE
+#define OMAP730_FPGA_FPGA_REV		(OMAP730_FPGA_BASE + 0x10)	/* FPGA Revision */
+#define OMAP730_FPGA_BOARD_REV		(OMAP730_FPGA_BASE + 0x12)	/* Board Revision */
+#define OMAP730_FPGA_GPIO		(OMAP730_FPGA_BASE + 0x14)	/* GPIO outputs */
+#define OMAP730_FPGA_LEDS		(OMAP730_FPGA_BASE + 0x16)	/* LEDs outputs */
+#define OMAP730_FPGA_MISC_INPUTS	(OMAP730_FPGA_BASE + 0x18)	/* Misc inputs */
+#define OMAP730_FPGA_LAN_STATUS		(OMAP730_FPGA_BASE + 0x1A)	/* LAN Status line */
+#define OMAP730_FPGA_LAN_RESET		(OMAP730_FPGA_BASE + 0x1C)	/* LAN Reset line */
+
+// LEDs definition on debug board (16 LEDs)
+#define OMAP730_FPGA_LED_CLAIMRELEASE	(1 << 15)
+#define OMAP730_FPGA_LED_STARTSTOP	(1 << 14)
+#define OMAP730_FPGA_LED_HALTED		(1 << 13)
+#define OMAP730_FPGA_LED_IDLE		(1 << 12)
+#define OMAP730_FPGA_LED_TIMER		(1 << 11)
+// cpu0 load-meter LEDs
+#define OMAP730_FPGA_LOAD_METER		(1 << 0)	// A bit of fun on our board ...
+#define OMAP730_FPGA_LOAD_METER_SIZE	11
+#define OMAP730_FPGA_LOAD_METER_MASK	((1 << OMAP730_FPGA_LOAD_METER_SIZE) - 1)
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE		D256M_1X16_4B
+#endif
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE	0xD8000000	/* VA */
+#define OMAP_FLASH_0_START	0x00000000	/* PA */
+#define OMAP_FLASH_0_SIZE	SZ_32M
+
+/* The Ethernet Controller IRQ is cascaded to MPU_EXT_nIRQ througb the FPGA */
+#define INT_ETHER		INT_730_MPU_EXT_NIRQ
+
+#define MAXIRQNUM		IH_BOARD_BASE
+#define MAXFIQNUM		MAXIRQNUM
+#define MAXSWINUM		MAXIRQNUM
+
+#define NR_IRQS			(MAXIRQNUM + 1)
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+#else
+#error "Only OMAP730 Perseus2 supported!"
+#endif
+
+#endif

include/asm-arm/arch-omap/board.h

+/*
+ *  linux/include/asm-arm/arch-omap/board.h
+ *
+ *  Information structures for board-specific data
+ *
+ *  Copyright (C) 2004	Nokia Corporation
+ *  Written by Juha Yrjl <juha.yrjola@nokia.com>
+ */
+
+#ifndef _OMAP_BOARD_H
+#define _OMAP_BOARD_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK		0x4f01
+#define OMAP_TAG_MMC		0x4f02
+#define OMAP_TAG_UART		0x4f03
+
+struct omap_clock_info {
+	/* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+	u8 system_clock_type;
+};
+
+struct omap_mmc_info {
+	u8 mmc_blocks;
+	s8 mmc1_power_pin, mmc2_power_pin;
+	s8 mmc1_switch_pin, mmc2_switch_pin;
+};
+
+struct omap_uart_info {
+	u8 console_uart;
+	u32 console_speed;
+};
+
+struct omap_board_info_entry {
+	u16 tag;
+	u16 len;
+	u8  data[0];
+};
+
+extern const void *__omap_get_per_info(u16 tag, size_t len);
+
+#define omap_get_per_info(tag, type) \
+	((const type *) __omap_get_per_info((tag), sizeof(type)))
+
+#endif

include/asm-arm/arch-omap/bus.h

@@ -43,6 +43,7 @@ struct omap_dev {
 	void		*mapbase;	/* OMAP physical address */
 	unsigned int	irq[6];		/* OMAP interrupts */
 	u64		*dma_mask;	/* Used by USB OHCI only */
+	u64		coherent_dma_mask;	/* Used by USB OHCI only */
 };
 
 #define OMAP_DEV(_d)	container_of((_d), struct omap_dev, dev)

include/asm-arm/arch-omap/hardware.h

@@ -47,66 +47,42 @@
  * I/O mapping
  * ----------------------------------------------------------------------------
  */
-#define IO_BASE			0xFFFB0000	/* Virtual */
+#define IO_PHYS			0xFFFB0000
+#define IO_OFFSET		0x01000000	/* Virtual IO = 0xfefb0000 */
+#define IO_VIRT			(IO_PHYS - IO_OFFSET)
 #define IO_SIZE			0x40000
-#define IO_START		0xFFFB0000	/* Physical */
+#define IO_ADDRESS(x)		((x) - IO_OFFSET)
 
 #define PCIO_BASE		0
 
-#define IO_ADDRESS(x)		((x))
+#define io_p2v(x)               ((x) - IO_OFFSET)
+#define io_v2p(x)               ((x) + IO_OFFSET)
 
-/*
- * ---------------------------------------------------------------------------
- * Processor differentiation
- * ---------------------------------------------------------------------------
- */
+#ifndef __ASSEMBLER__
 
-#ifdef CONFIG_ARCH_OMAP730
-#include "omap730.h"
-#define cpu_is_omap730()	(1)
-#else
-#define cpu_is_omap730()	(0)
-#endif
+/* 16 bit uses LDRH/STRH, base +/- offset_8 */
+typedef struct { volatile u16 offset[256]; } __regbase16;
+#define __REGV16(vaddr)		((__regbase16 *)((vaddr)&~0xff)) \
+					->offset[((vaddr)&0xff)>>1]
+#define __REG16(paddr)          __REGV16(io_p2v(paddr))
 
-#ifdef CONFIG_ARCH_OMAP1510
-#include "omap1510.h"
-#define cpu_is_omap1510()	(1)
-#else
-#define cpu_is_omap1510()	(0)
-#endif
+/* 8/32 bit uses LDR/STR, base +/- offset_12 */
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+#define __REGV8(vaddr)		((__regbase8  *)((paddr)&~4095)) \
+					->offset[((paddr)&4095)>>0]
+#define __REG8(paddr)		__REGV8(io_p2v(paddr))
 
-#ifdef CONFIG_ARCH_OMAP1610
-#include "omap1610.h"
-#define cpu_is_omap1610()	(1)
-#else
-#define cpu_is_omap1610()	(0)
-#endif
+typedef struct { volatile u32 offset[4096]; } __regbase32;
+#define __REGV32(vaddr)		((__regbase32 *)((vaddr)&~4095)) \
+					->offset[((vaddr)&4095)>>2]
+#define __REG32(paddr)		__REGV32(io_p2v(paddr))
 
-/*
- * ---------------------------------------------------------------------------
- * Board differentiation
- * ---------------------------------------------------------------------------
- */
-
-#ifdef CONFIG_OMAP_INNOVATOR
-#include "omap-innovator.h"
-#define omap_is_innovator()	(1)
 #else
-#define omap_is_innovator()	(0)
-#endif
 
-#ifdef CONFIG_MACH_OMAP_H2
-#include "omap-h2.h"
-#define omap_is_h2()		(1)
-#else
-#define omap_is_h2()		(0)
-#endif
+#define __REG8(paddr)		io_p2v(paddr)
+#define __REG16(paddr)		io_p2v(paddr)
+#define __REG32(paddr)		io_p2v(paddr)
 
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
-#include "omap-perseus2.h"
-#define omap_is_perseus2()	(1)
-#else
-#define omap_is_perseus2()	(0)
 #endif
 
 /*
@@ -117,35 +93,19 @@
  * ---------------------------------------------------------------------------
  */
 
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP_DSP_BASE		0xE0000000
-#define OMAP_DSP_SIZE		0x50000
-#define OMAP_DSP_START		0xE0000000
-
-#define OMAP_DSPREG_BASE	0xE1000000
-#define OMAP_DSPREG_SIZE	SZ_128K
-#define OMAP_DSPREG_START	0xE1000000
-
 /*
  * ----------------------------------------------------------------------------
  * Clocks
  * ----------------------------------------------------------------------------
  */
 #define CLKGEN_RESET_BASE	(0xfffece00)
-#define ARM_CKCTL		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
-#define ARM_IDLECT1		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
-#define ARM_IDLECT2		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
-#define ARM_EWUPCT		(volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
-#define ARM_RSTCT1		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
-#define ARM_RSTCT2		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
-#define ARM_SYSST		(volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
+#define ARM_CKCTL		(CLKGEN_RESET_BASE + 0x0)
+#define ARM_IDLECT1		(CLKGEN_RESET_BASE + 0x4)
+#define ARM_IDLECT2		(CLKGEN_RESET_BASE + 0x8)
+#define ARM_EWUPCT		(CLKGEN_RESET_BASE + 0xC)
+#define ARM_RSTCT1		(CLKGEN_RESET_BASE + 0x10)
+#define ARM_RSTCT2		(CLKGEN_RESET_BASE + 0x14)
+#define ARM_SYSST		(CLKGEN_RESET_BASE + 0x18)
 
 #define CK_RATEF		1
 #define CK_IDLEF		2
@@ -154,19 +114,19 @@
 #define SETARM_IDLE_SHIFT
 
 /* DPLL control registers */
-#define DPLL_CTL_REG		(volatile __u16 *)(0xfffecf00)
-#define CK_DPLL1		(volatile __u16 *)(0xfffecf00)
+#define DPLL_CTL_REG		(0xfffecf00)
+#define CK_DPLL1		(0xfffecf00)
 
 /* ULPD */
 #define ULPD_REG_BASE		(0xfffe0800)
-#define ULPD_IT_STATUS_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x14)
-#define ULPD_CLOCK_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x30)
-#define ULPD_SOFT_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x34)
-#define ULPD_DPLL_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x3c)
-#define ULPD_STATUS_REQ_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x40)
-#define ULPD_APLL_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x4c)
-#define ULPD_POWER_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x50)
-#define ULPD_CAM_CLK_CTRL_REG	(volatile __u16 *)(ULPD_REG_BASE + 0x7c)
+#define ULPD_IT_STATUS_REG	(ULPD_REG_BASE + 0x14)
+#define ULPD_CLOCK_CTRL_REG	(ULPD_REG_BASE + 0x30)
+#define ULPD_SOFT_REQ_REG	(ULPD_REG_BASE + 0x34)
+#define ULPD_DPLL_CTRL_REG	(ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ_REG	(ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL_REG	(ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL_REG	(ULPD_REG_BASE + 0x50)
+#define ULPD_CAM_CLK_CTRL_REG	(ULPD_REG_BASE + 0x7c)
 
 /*
  * ---------------------------------------------------------------------------
@@ -261,6 +221,7 @@
  * ----------------------------------------------------------------------------
  */
 #define MOD_CONF_CTRL_0		0xfffe1080
+#define MOD_CONF_CTRL_1		0xfffe1110
 
 /*
  * ----------------------------------------------------------------------------
@@ -315,13 +276,89 @@
  * ----------------------------------------------------------------------------
  */
 /*  MPUI Interface Registers */
-#define MPUI_CTRL_REG		(volatile __u32 *)(0xfffec900)
-#define MPUI_DEBUG_ADDR		(volatile __u32 *)(0xfffec904)
-#define MPUI_DEBUG_DATA		(volatile __u32 *)(0xfffec908)
-#define MPUI_DEBUG_FLAG		(volatile __u16 *)(0xfffec90c)
-#define MPUI_STATUS_REG		(volatile __u16 *)(0xfffec910)
-#define MPUI_DSP_STATUS_REG	(volatile __u16 *)(0xfffec914)
-#define MPUI_DSP_BOOT_CONFIG	(volatile __u16 *)(0xfffec918)
-#define MPUI_DSP_API_CONFIG	(volatile __u16 *)(0xfffec91c)
+#define MPUI_CTRL_REG		(0xfffec900)
+#define MPUI_DEBUG_ADDR		(0xfffec904)
+#define MPUI_DEBUG_DATA		(0xfffec908)
+#define MPUI_DEBUG_FLAG		(0xfffec90c)
+#define MPUI_STATUS_REG		(0xfffec910)
+#define MPUI_DSP_STATUS_REG	(0xfffec914)
+#define MPUI_DSP_BOOT_CONFIG	(0xfffec918)
+#define MPUI_DSP_API_CONFIG	(0xfffec91c)
+
+
+#ifndef __ASSEMBLER__
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor differentiation
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_ID_REG		__REG32(0xfffed404)
+
+#ifdef CONFIG_ARCH_OMAP730
+#include "omap730.h"
+#define cpu_is_omap730()	(((OMAP_ID_REG >> 12) & 0xffff) == 0xB55F)
+#else
+#define cpu_is_omap730()	0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+#include "omap1510.h"
+#define cpu_is_omap1510()	(((OMAP_ID_REG >> 12) & 0xffff) == 0xB470)
+#else
+#define cpu_is_omap1510()	0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1610
+#include "omap1610.h"
+#define cpu_is_omap1710()       (((OMAP_ID_REG >> 12) & 0xffff) == 0xB5F7)
+/* Detect 1710 as 1610 for now */
+#define cpu_is_omap1610()	(((OMAP_ID_REG >> 12) & 0xffff) == 0xB576 || \
+				 cpu_is_omap1710())
+#else
+#define cpu_is_omap1610()	0
+#define cpu_is_omap1710()	0
+#endif
+
+#ifdef CONFIG_ARCH_OMAP5912
+#include "omap5912.h"
+#define cpu_is_omap5912()	(((OMAP_ID_REG >> 12) & 0xffff) == 0xB58C)
+#else
+#define cpu_is_omap5912()	0
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board differentiation
+ * ---------------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+#include "board-innovator.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+#include "board-h2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#include "board-perseus2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H3
+#include "board-h3.h"
+#error "Support for H3 board not yet implemented."
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H4
+#include "board-h4.h"
+#error "Support for H4 board not yet implemented."
+#endif
+
+#ifdef CONFIG_MACH_OMAP_OSK
+#include "board-osk.h"
+#endif
+
+#endif /* !__ASSEMBLER__ */
 
 #endif	/* __ASM_ARCH_OMAP_HARDWARE_H */

include/asm-arm/arch-omap/io.h

@@ -21,4 +21,21 @@
 #define __mem_pci(a)		((unsigned long)(a))
 #define __mem_isa(a)		((unsigned long)(a))
 
+/*
+ * Functions to access the OMAP IO region
+ *
+ * NOTE: - Use omap_read/write[bwl] for physical register addresses
+ *	 - Use __raw_read/write[bwl]() for virtual register addresses
+ *	 - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
+ *	 - DO NOT use hardcoded virtual addresses to allow changing the
+ *	   IO address space again if needed
+ */
+#define omap_readb(a)		(*(volatile unsigned char  *)IO_ADDRESS(a))
+#define omap_readw(a)		(*(volatile unsigned short *)IO_ADDRESS(a))
+#define omap_readl(a)		(*(volatile unsigned int   *)IO_ADDRESS(a))
+
+#define omap_writeb(v,a)	(*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
+#define omap_writew(v,a)	(*(volatile unsigned short *)IO_ADDRESS(a) = (v))
+#define omap_writel(v,a)	(*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
+
 #endif

include/asm-arm/arch-omap/irqs.h

@@ -259,4 +259,8 @@ extern void omap_init_irq(void);
  */
 #include <asm/arch/hardware.h>
 
+#ifndef NR_IRQS
+#define NR_IRQS                 256
+#endif
+
 #endif

include/asm-arm/arch-omap/mux.h

@@ -40,7 +40,8 @@
 #ifndef __ASM_ARCH_MUX_H
 #define __ASM_ARCH_MUX_H
 
-#define PU_PD_SEL_NA	0	/* No pu_pd reg availabe */
+#define PU_PD_SEL_NA		0	/* No pu_pd reg available */
+#define PULL_DWN_CTRL_NA	0	/* No pull-down control needed */
 
 #define DEBUG_MUX
 
@@ -278,9 +279,12 @@ typedef enum {
 	E19_1610_KBR4,
 	N19_1610_KBR5,
 
+	/* Power management */
+	T20_1610_LOW_PWR,
+
 } reg_cfg_t;
 
-#ifdef __MUX_C__
+#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
 
 /*
  * Table of various FUNC_MUX and PULL_DWN combinations for each device.
@@ -401,14 +405,14 @@ MUX_CFG("U18_1610_UWIRE_SDI",	 8,    0,    0,	  1,  18,   0,	  1,	 1,  1)
 MUX_CFG("W21_1610_UWIRE_SDO",	 8,    3,    0,	  1,  19,   0,	  1,	 1,  1)
 MUX_CFG("N14_1610_UWIRE_CS0",	 8,    9,    1,	  1,  21,   0,	  1,	 1,  1)
 MUX_CFG("P15_1610_UWIRE_CS3",	 8,   12,    1,	  1,  22,   0,	  1,	 1,  1)
-MUX_CFG("N15_1610_UWIRE_CS1",	 7,   18,    2,	  0,   0,   0,	  0,	 0,  0)
+MUX_CFG("N15_1610_UWIRE_CS1",	 7,   18,    2,	 NA,   0,   0,	 NA,	 0,  0)
 
 /* First MMC interface, same on 1510 and 1610 */
 MUX_CFG("MMC_CMD",		 A,   27,    0,	  2,  15,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT1",		 A,   24,    0,	  2,  14,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT2",		 A,   18,    0,	  2,  12,   1,	  2,	 1,  1)
 MUX_CFG("MMC_DAT0",		 B,    0,    0,	  2,  16,   1,	  2,	 1,  1)
-MUX_CFG("MMC_CLK",		 A,   21,    0,	  0,   0,   0,	  0,	 0,  1)
+MUX_CFG("MMC_CLK",		 A,   21,    0,	 NA,   0,   0,	 NA,	 0,  1)
 MUX_CFG("MMC_DAT3",		10,   15,    0,	  3,   8,   1,	  3,	 1,  1)
 
 /* OMAP-1610 USB0 alternate configuration */
@@ -422,12 +426,12 @@ MUX_CFG("V9_USB0_SPEED",	 B,  12,     5,	  2,  20,   0,	  2,	 0,  1)
 MUX_CFG("Y10_USB0_SUSP",	 B,   3,     5,	  2,  17,   0,	  2,	 0,  1)
 
 /* USB2 interface */
-MUX_CFG("W9_USB2_TXEN",		 B,   9,     1,	  0,   0,   0,	 NA,	 0,  1)
-MUX_CFG("AA9_USB2_VP",		 B,   6,     1,	  0,   0,   0,	 NA,	 0,  1)
-MUX_CFG("Y5_USB2_RCV",		 C,  21,     1,	  0,   0,   0,	 NA,	 0,  1)
-MUX_CFG("R8_USB2_VM",		 C,  18,     1,	  0,   0,   0,	 NA,	 0,  1)
-MUX_CFG("V6_USB2_TXD",		 C,  27,     2,	  0,   0,   0,	 NA,	 0,  1)
-MUX_CFG("W5_USB2_SE0",		 C,  24,     2,	  0,   0,   0,	 NA,	 0,  1)
+MUX_CFG("W9_USB2_TXEN",		 B,   9,     1,	 NA,   0,   0,	 NA,	 0,  1)
+MUX_CFG("AA9_USB2_VP",		 B,   6,     1,	 NA,   0,   0,	 NA,	 0,  1)
+MUX_CFG("Y5_USB2_RCV",		 C,  21,     1,	 NA,   0,   0,	 NA,	 0,  1)
+MUX_CFG("R8_USB2_VM",		 C,  18,     1,	 NA,   0,   0,	 NA,	 0,  1)
+MUX_CFG("V6_USB2_TXD",		 C,  27,     2,	 NA,   0,   0,	 NA,	 0,  1)
+MUX_CFG("W5_USB2_SE0",		 C,  24,     2,	 NA,   0,   0,	 NA,	 0,  1)
 
 
 /* UART1 */
@@ -437,8 +441,8 @@ MUX_CFG("R14_1610_UART1_CTS",	 9,  15,     0,	  2,   1,   0,	  2,	 1,  1)
 MUX_CFG("AA15_1610_UART1_RTS",	 9,  12,     1,	  2,   0,   0,	  2,	 0,  1)
 
 /* I2C interface */
-MUX_CFG("I2C_SCL",		 7,  24,     0,	  0,   0,   0,	  0,	 0,  0)
-MUX_CFG("I2C_SDA",		 7,  27,     0,	  0,   0,   0,	  0,	 0,  0)
+MUX_CFG("I2C_SCL",		 7,  24,     0,	 NA,   0,   0,	 NA,	 0,  0)
+MUX_CFG("I2C_SDA",		 7,  27,     0,	 NA,   0,   0,	 NA,	 0,  0)
 
 /* Keypad */
 MUX_CFG("F18_1610_KBC0",	 3,  15,     0,	  0,   5,   1,	  0,	 0,  0)
@@ -453,6 +457,8 @@ MUX_CFG("E20_1610_KBR3",	 3,   21,    0,	  0,   7,   1,	  0,	 1,  0)
 MUX_CFG("E19_1610_KBR4",	 3,   18,    0,	  0,   6,   1,	  0,	 1,  0)
 MUX_CFG("N19_1610_KBR5",	 6,  12,     1,	  1,   2,   1,	  1,	 1,  0)
 
+/* Power management */
+MUX_CFG("T20_1610_LOW_PWR",	 7,   12,    1,	  0,   0,   0,   NA,	 0,  0)
 };
 
 #endif	/* __MUX_C__ */

include/asm-arm/arch-omap/omap1510.h

@@ -36,19 +36,27 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP_SRAM_BASE		0xD0000000
-#define OMAP_SRAM_SIZE		(SZ_128K + SZ_64K)
-#define OMAP_SRAM_START		0x20000000
+#define OMAP1510_SRAM_BASE	0xD0000000
+#define OMAP1510_SRAM_SIZE	(SZ_128K + SZ_64K)
+#define OMAP1510_SRAM_START	0x20000000
 
-#define OMAP_MCBSP1_BASE	0xE1011000
-#define OMAP_MCBSP1_SIZE	SZ_4K
-#define OMAP_MCBSP1_START	0xE1011000
+#define OMAP1510_MCBSP1_BASE	0xE1011000
+#define OMAP1510_MCBSP1_SIZE	SZ_4K
+#define OMAP1510_MCBSP1_START	0xE1011000
 
-#define OMAP_MCBSP2_BASE	0xFFFB1000
+#define OMAP1510_MCBSP2_BASE	0xFFFB1000
 
-#define OMAP_MCBSP3_BASE	0xE1017000
-#define OMAP_MCBSP3_SIZE	SZ_4K
-#define OMAP_MCBSP3_START	0xE1017000
+#define OMAP1510_MCBSP3_BASE	0xE1017000
+#define OMAP1510_MCBSP3_SIZE	SZ_4K
+#define OMAP1510_MCBSP3_START	0xE1017000
+
+#define OMAP1510_DSP_BASE	0xE0000000
+#define OMAP1510_DSP_SIZE	0x28000
+#define OMAP1510_DSP_START	0xE0000000
+
+#define OMAP1510_DSPREG_BASE	0xE1000000
+#define OMAP1510_DSPREG_SIZE	SZ_128K
+#define OMAP1510_DSPREG_START	0xE1000000
 
 #endif /*  __ASM_ARCH_OMAP1510_H */
 

include/asm-arm/arch-omap/omap1610.h

@@ -36,9 +36,22 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP_SRAM_BASE		0xD0000000
-#define OMAP_SRAM_SIZE		(SZ_16K)
-#define OMAP_SRAM_START		0x20000000
+#define OMAP1610_SRAM_BASE	0xD0000000
+#define OMAP1610_SRAM_SIZE	(SZ_16K)
+#define OMAP1610_SRAM_START	0x20000000
+
+#define OMAP1610_DSP_BASE	0xE0000000
+#define OMAP1610_DSP_SIZE	0x28000
+#define OMAP1610_DSP_START	0xE0000000
+
+#define OMAP1610_DSPREG_BASE	0xE1000000
+#define OMAP1610_DSPREG_SIZE	SZ_128K
+#define OMAP1610_DSPREG_START	0xE1000000
+
+#define OMAP_IH2_0_BASE          0xfffe0000
+#define OMAP_IH2_1_BASE          0xfffe0100
+#define OMAP_IH2_2_BASE          0xfffe0200
+#define OMAP_IH2_3_BASE          0xfffe0300
 
 /*
  * ----------------------------------------------------------------------------
@@ -46,14 +59,14 @@
  * ----------------------------------------------------------------------------
  */
 
-#define OMAP_RESET_CONTROL	0xfffe1140
-#define ARM_IDLECT3		(CLKGEN_RESET_BASE + 0x24)
-#define CONF_VOLTAGE_CTRL_0	0xfffe1060
-#define CONF_VOLTAGE_VDDSHV6	(1 << 8)
-#define CONF_VOLTAGE_VDDSHV7	(1 << 9)
-#define CONF_VOLTAGE_VDDSHV8	(1 << 10)
-#define CONF_VOLTAGE_VDDSHV9	(1 << 11)
-#define SUBLVDS_CONF_VALID	(1 << 13)
+#define OMAP1610_RESET_CONTROL		0xfffe1140
+#define OMAP1610_ARM_IDLECT3		(CLKGEN_RESET_BASE + 0x24)
+#define OMAP1610_CONF_VOLTAGE_CTRL_0	0xfffe1060
+#define OMAP1610_CONF_VOLTAGE_VDDSHV6	(1 << 8)
+#define OMAP1610_CONF_VOLTAGE_VDDSHV7	(1 << 9)
+#define OMAP1610_CONF_VOLTAGE_VDDSHV8	(1 << 10)
+#define OMAP1610_CONF_VOLTAGE_VDDSHV9	(1 << 11)
+#define OMAP1610_SUBLVDS_CONF_VALID	(1 << 13)
 
 /*
  * ---------------------------------------------------------------------------
@@ -61,13 +74,13 @@
  * ---------------------------------------------------------------------------
  */
 
-#define OMAP_TIPB_SWITCH	0xfffbc800
-#define TIPB_BRIDGE_INT		0xfffeca00	/* Private TIPB_CNTL */
-#define PRIVATE_MPU_TIPB_CNTL	0xfffeca08
-#define TIPB_BRIDGE_EXT		0xfffed300	/* Public (Shared) TIPB_CNTL */
-#define PUBLIC_MPU_TIPB_CNTL	0xfffed308
-#define TIPB_SWITCH_CFG		OMAP_TIPB_SWITCH
-#define MMCSD2_SSW_MPU_CONF	(TIPB_SWITCH_CFG + 0x160)
+#define OMAP1610_TIPB_SWITCH		0xfffbc800
+#define OMAP1610_TIPB_BRIDGE_INT	0xfffeca00	/* Private TIPB_CNTL */
+#define OMAP1610_PRIVATE_MPU_TIPB_CNTL	0xfffeca08
+#define OMAP1610_TIPB_BRIDGE_EXT	0xfffed300	/* Public (Shared) TIPB_CNTL */
+#define OMAP1610_PUBLIC_MPU_TIPB_CNTL	0xfffed308
+#define OMAP1610_TIPB_SWITCH_CFG	OMAP_TIPB_SWITCH
+#define OMAP1610_MMCSD2_SSW_MPU_CONF	(TIPB_SWITCH_CFG + 0x160)
 
 #endif /*  __ASM_ARCH_OMAP1610_H */
 

include/asm-arm/arch-omap/omap5912.h

+/* linux/include/asm-arm/arch-omap/omap5912.h
+ *
+ * Hardware definitions for TI OMAP5912 processor.
+ *
+ * Written by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP5912_H
+#define __ASM_ARCH_OMAP5912_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+/* OMAP5912 internal SRAM size is 250kByte */
+#define OMAP5912_SRAM_BASE	0xD0000000
+#define OMAP5912_SRAM_SIZE	0x3E800
+#define OMAP5912_SRAM_START	0x20000000
+
+#define OMAP5912_DSP_BASE	0xE0000000
+#define OMAP5912_DSP_SIZE	0x50000
+#define OMAP5912_DSP_START	0xE0000000
+
+#define OMAP5912_DSPREG_BASE	0xE1000000
+#define OMAP5912_DSPREG_SIZE	SZ_128K
+#define OMAP5912_DSPREG_START	0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP5912_ARM_IDLECT3		(CLKGEN_RESET_BASE + 0x24)
+
+#endif /*  __ASM_ARCH_OMAP5912_H */
+

include/asm-arm/arch-omap/omap730.h

@@ -36,15 +36,77 @@
 
 /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
 
-#define OMAP_SRAM_BASE		0xD0000000
-#define OMAP_SRAM_SIZE		(SZ_128K + SZ_64K + SZ_8K)
-#define OMAP_SRAM_START		0x20000000
+#define OMAP730_SRAM_BASE	0xD0000000
+#define OMAP730_SRAM_SIZE	(SZ_128K + SZ_64K + SZ_8K)
+#define OMAP730_SRAM_START	0x20000000
 
-#define OMAP_MCBSP1_BASE	0xfffb1000
-#define OMAP_MCBSP1_SIZE	(SZ_1K * 2)
-#define OMAP_MCBSP1_START	0xfffb1000
+#define OMAP730_MCBSP1_BASE	0xfffb1000
+#define OMAP730_MCBSP1_SIZE	(SZ_1K * 2)
+#define OMAP730_MCBSP1_START	0xfffb1000
 
-#define OMAP_MCBSP2_BASE	0xfffb1800
+#define OMAP730_MCBSP2_BASE	0xfffb1800
+
+#define OMAP730_DSP_BASE	0xE0000000
+#define OMAP730_DSP_SIZE	0x50000
+#define OMAP730_DSP_START	0xE0000000
+
+#define OMAP730_DSPREG_BASE	0xE1000000
+#define OMAP730_DSPREG_SIZE	SZ_128K
+#define OMAP730_DSPREG_START	0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_CONFIG_BASE	0xfffe1000
+#define OMAP730_IO_CONF_0	0xfffe1070
+#define OMAP730_IO_CONF_1	0xfffe1074
+#define OMAP730_IO_CONF_2	0xfffe1078
+#define OMAP730_IO_CONF_3	0xfffe107c
+#define OMAP730_IO_CONF_4	0xfffe1080
+#define OMAP730_IO_CONF_5	0xfffe1084
+#define OMAP730_IO_CONF_6	0xfffe1088
+#define OMAP730_IO_CONF_7	0xfffe108c
+#define OMAP730_IO_CONF_8	0xfffe1090
+#define OMAP730_IO_CONF_9	0xfffe1094
+#define OMAP730_IO_CONF_10	0xfffe1098
+#define OMAP730_IO_CONF_11	0xfffe109c
+#define OMAP730_IO_CONF_12	0xfffe10a0
+#define OMAP730_IO_CONF_13	0xfffe10a4
+
+#define OMAP730_MODE_1		0xfffe1010
+#define OMAP730_MODE_2		0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP730_MODE2_OFFSET	0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_FLASH_CFG_0	0xfffecc10
+#define OMAP730_FLASH_ACFG_0	0xfffecc50
+#define OMAP730_FLASH_CFG_1	0xfffecc14
+#define OMAP730_FLASH_ACFG_1	0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_ICR_BASE	0xfffbb800
+#define OMAP730_DSP_M_CTL	0xfffbb804
+#define OMAP730_DSP_MMU_BASE	0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_PCC_UPLD_CTRL_REG_BASE	(0xfffe0900)
+#define OMAP730_PCC_UPLD_CTRL_REG	(OMAP730_PCC_UPLD_CTRL_REG_BASE + 0x00)
 
 #endif /*  __ASM_ARCH_OMAP730_H */
 

include/asm-arm/arch-omap/pm.h

@@ -35,8 +35,8 @@
  * More ones like CP and general purpose register values are preserved
  * with the stack pointer in sleep.S.
  */
-#ifndef __ASM_ARCH_OMAP1510_PM_H
-#define __ASM_ARCH_OMAP1510_PM_H
+#ifndef __ASM_ARCH_OMAP_PM_H
+#define __ASM_ARCH_OMAP_PM_H
 
 #define ARM_REG_BASE		(0xfffece00)
 #define ARM_ASM_IDLECT1		(ARM_REG_BASE + 0x4)
@@ -50,29 +50,53 @@
 #define TCMIF_BASE		0xfffecc00
 #define EMIFS_ASM_CONFIG_REG	(TCMIF_BASE + 0x0c)
 #define EMIFF_ASM_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
-#define IRQ_MIR1	(volatile unsigned int *)(OMAP_IH1_BASE + IRQ_MIR)
-#define IRQ_MIR2	(volatile unsigned int *)(OMAP_IH2_BASE + IRQ_MIR)
+#define IRQ_MIR1		(OMAP_IH1_BASE + IRQ_MIR)
+
+#ifdef CONFIG_ARCH_OMAP1510
+#define IRQ_MIR2		(OMAP_IH2_BASE + IRQ_MIR)
+#else /* CONFIG_ARCH_OMAP1610 */
+#define IRQ_MIR2_0		(OMAP_IH2_0_BASE + IRQ_MIR)
+#define IRQ_MIR2_1		(OMAP_IH2_1_BASE + IRQ_MIR)
+#define IRQ_MIR2_2		(OMAP_IH2_2_BASE + IRQ_MIR)
+#define IRQ_MIR2_3		(OMAP_IH2_3_BASE + IRQ_MIR)
+#endif
 
-#define IDLE_WAIT_CYCLES		0x000000ff
+#define IDLE_WAIT_CYCLES		0x00000fff
 #define PERIPHERAL_ENABLE		0x2
+
+#ifdef CONFIG_ARCH_OMAP1510
+#define DEEP_SLEEP_REQUEST		0x0ec7
 #define BIG_SLEEP_REQUEST		0x0cc5
 #define IDLE_LOOP_REQUEST		0x0c00
+#define IDLE_CLOCK_DOMAINS		0x2
+#else /* CONFIG_ARCH_OMAP1610 */
+#define DEEP_SLEEP_REQUEST		0x17c7
+#define BIG_SLEEP_REQUEST		TBD
+#define IDLE_LOOP_REQUEST		0x0400
+#define IDLE_CLOCK_DOMAINS		0x09c7
+#endif
+
 #define SELF_REFRESH_MODE		0x0c000001
 #define IDLE_EMIFS_REQUEST		0xc
-#define IDLE_CLOCK_DOMAINS		0x2
 #define MODEM_32K_EN			0x1
 
 #ifndef __ASSEMBLER__
-extern void omap1510_pm_idle(void);
+extern void omap_pm_idle(void);
 extern void omap_pm_suspend(void);
-extern int omap1510_cpu_suspend(void);
-extern int omap1510_idle_loop_suspend(void);
+extern int omap_cpu_suspend(unsigned short, unsigned short);
+extern int omap_idle_loop_suspend(void);
 extern struct async_struct *omap_pm_sercons;
 extern unsigned int serial_in(struct async_struct *, int);
 extern unsigned int serial_out(struct async_struct *, int, int);
 
-#define OMAP1510_SRAM_IDLE_SUSPEND	0xd002F000
-#define OMAP1510_SRAM_API_SUSPEND	0xd002F200
+#ifdef CONFIG_ARCH_OMAP1510
+#define OMAP_SRAM_IDLE_SUSPEND	0xd002F000
+#define OMAP_SRAM_API_SUSPEND	0xd002F200
+#else /* CONFIG_ARCH_OMAP1610 */
+#define OMAP_SRAM_IDLE_SUSPEND	0xd0000400
+#define OMAP_SRAM_API_SUSPEND	0xd0000600
+#endif
+
 #define CPU_SUSPEND_SIZE	200
 #define ARM_REG_BASE		(0xfffece00)
 #define ARM_ASM_IDLECT1		(ARM_REG_BASE + 0x4)
@@ -82,10 +106,17 @@ extern unsigned int serial_out(struct async_struct *, int, int);
 #define ARM_ASM_SYSST		(ARM_REG_BASE + 0x18)
 
 #define TCMIF_BASE		0xfffecc00
-#define PM_EMIFS_CONFIG_REG	   (volatile unsigned int *)(TCMIF_BASE + 0x0c)
-#define PM_EMIFF_SDRAM_CONFIG	   (volatile unsigned int *)(TCMIF_BASE + 0x20)
-
-#define ULPD_LOW_POWER_REQ		0x3
+#define PM_EMIFS_CONFIG_REG	(TCMIF_BASE + 0x0c)
+#define PM_EMIFF_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
+#define FUNC_MUX_CTRL_LOW_PWR	(0xfffe1020)
+
+#ifdef CONFIG_ARCH_OMAP1510
+#define ULPD_LOW_POWER_REQ             0x0001
+#else /* CONFIG_ARCH_OMAP1610 */
+#define ULPD_LOW_POWER_REQ             0x3
+#endif
+#define ULPD_LOW_PWR                   0x1000
+#define ULPD_LOW_POWER_EN              0x0001
 
 #define DSP_IDLE_DELAY			10
 #define DSP_IDLE			0x0040
@@ -98,16 +129,16 @@ extern unsigned int serial_out(struct async_struct *, int, int);
 #define EMIFF_CONFIG_REG		EMIFF_SDRAM_CONFIG
 
 
-#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = (unsigned short)*x
-#define ARM_RESTORE(x) *x = (unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x]
+#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readw(x)
+#define ARM_RESTORE(x) omap_writew((unsigned short)arm_sleep_save[ARM_SLEEP_SAVE_##x], x)
 #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
 
-#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = (unsigned short)*x
-#define ULPD_RESTORE(x) *x = (unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
+#define ULPD_RESTORE(x) omap_writew((unsigned short)ulpd_sleep_save[ULPD_SLEEP_SAVE_##x], x)
 #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
 
-#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = (unsigned int)*x
-#define MPUI_RESTORE(x) *x = (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
+#define MPUI_SAVE(x) mpui_sleep_save[MPUI_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI_RESTORE(x) omap_writel((unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x], x)
 #define MPUI_SHOW(x) (unsigned int)mpui_sleep_save[MPUI_SLEEP_SAVE_##x]
 
 enum arm_save_state {
@@ -124,7 +155,7 @@ enum arm_save_state {
 };
 
 enum ulpd_save_state {
-	ULDP_SLEEP_SAVE_START = 0,
+	ULPD_SLEEP_SAVE_START = 0,
 	ULPD_SLEEP_SAVE_ULPD_IT_STATUS_REG, ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL_REG,
 	ULPD_SLEEP_SAVE_ULPD_SOFT_REQ_REG, ULPD_SLEEP_SAVE_ULPD_STATUS_REQ_REG,
 	ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL_REG, ULPD_SLEEP_SAVE_ULPD_POWER_CTRL_REG,
@@ -140,7 +171,15 @@ enum mpui_save_state {
 	MPUI_SLEEP_SAVE_MPUI_DSP_STATUS_REG,
 	MPUI_SLEEP_SAVE_PM_EMIFF_SDRAM_CONFIG,
 	MPUI_SLEEP_SAVE_PM_EMIFS_CONFIG_REG,
-	MPUI_SLEEP_SAVE_IRQ_MIR1, MPUI_SLEEP_SAVE_IRQ_MIR2,
+	MPUI_SLEEP_SAVE_IRQ_MIR1,
+#ifdef CONFIG_ARCH_OMAP1510
+	MPUI_SLEEP_SAVE_IRQ_MIR2,
+#else /* CONFIG_ARCH_OMAP1610 */
+	MPUI_SLEEP_SAVE_IRQ_MIR2_0,
+	MPUI_SLEEP_SAVE_IRQ_MIR2_1,
+	MPUI_SLEEP_SAVE_IRQ_MIR2_2,
+	MPUI_SLEEP_SAVE_IRQ_MIR2_3,
+#endif
 
 	MPUI_SLEEP_SAVE_SIZE
 };

include/asm-arm/arch-omap/serial.h

@@ -9,136 +9,17 @@
 #ifndef __ASM_ARCH_SERIAL_H
 #define __ASM_ARCH_SERIAL_H
 
-
-#define OMAP1510_UART1_BASE	(unsigned char *)0xfffb0000
-#define OMAP1510_UART2_BASE	(unsigned char *)0xfffb0800
-#define OMAP1510_UART3_BASE	(unsigned char *)0xfffb9800
-
-#define OMAP730_UART1_BASE	(unsigned char *)0xfffb0000
-#define OMAP730_UART2_BASE	(unsigned char *)0xfffb0800
-
-#if defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP1610)
-#define OMAP_SERIAL_REG_SHIFT 2
-#else
-#define OMAP_SERIAL_REG_SHIFT 0
-#endif
-
+#define OMAP_UART1_BASE		(unsigned char *)0xfffb0000
+#define OMAP_UART2_BASE		(unsigned char *)0xfffb0800
+#define OMAP_UART3_BASE		(unsigned char *)0xfffb9800
 
 #ifndef __ASSEMBLY__
 
 #include <asm/arch/hardware.h>
 #include <asm/irq.h>
 
-
-/* UART3 Registers Maping through MPU bus */
-#define OMAP_MPU_UART3_BASE	0xFFFB9800	/* UART3 through MPU bus */
-#define UART3_RHR		(OMAP_MPU_UART3_BASE + 0)
-#define UART3_THR		(OMAP_MPU_UART3_BASE + 0)
-#define UART3_DLL		(OMAP_MPU_UART3_BASE + 0)
-#define UART3_IER		(OMAP_MPU_UART3_BASE + 4)
-#define UART3_DLH		(OMAP_MPU_UART3_BASE + 4)
-#define UART3_IIR		(OMAP_MPU_UART3_BASE + 8)
-#define UART3_FCR		(OMAP_MPU_UART3_BASE + 8)
-#define UART3_EFR		(OMAP_MPU_UART3_BASE + 8)
-#define UART3_LCR		(OMAP_MPU_UART3_BASE + 0x0C)
-#define UART3_MCR		(OMAP_MPU_UART3_BASE + 0x10)
-#define UART3_XON1_ADDR1	(OMAP_MPU_UART3_BASE + 0x10)
-#define UART3_XON2_ADDR2	(OMAP_MPU_UART3_BASE + 0x14)
-#define UART3_LSR		(OMAP_MPU_UART3_BASE + 0x14)
-#define UART3_TCR		(OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_MSR		(OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_XOFF1		(OMAP_MPU_UART3_BASE + 0x18)
-#define UART3_XOFF2		(OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_SPR		(OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_TLR		(OMAP_MPU_UART3_BASE + 0x1C)
-#define UART3_MDR1		(OMAP_MPU_UART3_BASE + 0x20)
-#define UART3_MDR2		(OMAP_MPU_UART3_BASE + 0x24)
-#define UART3_SFLSR		(OMAP_MPU_UART3_BASE + 0x28)
-#define UART3_TXFLL		(OMAP_MPU_UART3_BASE + 0x28)
-#define UART3_RESUME		(OMAP_MPU_UART3_BASE + 0x2C)
-#define UART3_TXFLH		(OMAP_MPU_UART3_BASE + 0x2C)
-#define UART3_SFREGL		(OMAP_MPU_UART3_BASE + 0x30)
-#define UART3_RXFLL		(OMAP_MPU_UART3_BASE + 0x30)
-#define UART3_SFREGH		(OMAP_MPU_UART3_BASE + 0x34)
-#define UART3_RXFLH		(OMAP_MPU_UART3_BASE + 0x34)
-#define UART3_BLR		(OMAP_MPU_UART3_BASE + 0x38)
-#define UART3_ACREG		(OMAP_MPU_UART3_BASE + 0x3C)
-#define UART3_DIV16		(OMAP_MPU_UART3_BASE + 0x3C)
-#define UART3_SCR		(OMAP_MPU_UART3_BASE + 0x40)
-#define UART3_SSR		(OMAP_MPU_UART3_BASE + 0x44)
-#define UART3_EBLR		(OMAP_MPU_UART3_BASE + 0x48)
-#define UART3_OSC_12M_SEL	(OMAP_MPU_UART3_BASE + 0x4C)
-#define UART3_MVR		(OMAP_MPU_UART3_BASE + 0x50)
-
-#ifdef CONFIG_ARCH_OMAP1510
-#define BASE_BAUD (12000000/16)
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1610
-#define BASE_BAUD (48000000/16)
-#endif
-
-#ifdef CONFIG_ARCH_OMAP730
-#define BASE_BAUD (48000000/16)
-
-#define RS_TABLE_SIZE		2
-
-#define STD_COM_FLAGS	(ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS	\
-	{	\
-		.uart =			PORT_OMAP,		\
-		.baud_base =		BASE_BAUD,		\
-		.iomem_base =		OMAP730_UART1_BASE,	\
-		.iomem_reg_shift =	0,			\
-		.io_type =		SERIAL_IO_MEM,		\
-		.irq =			INT_UART1,		\
-		.flags =			STD_COM_FLAGS,		\
-	}, {	\
-		.uart =			PORT_OMAP,		\
-		.baud_base =		BASE_BAUD,		\
-		.iomem_base =		OMAP730_UART2_BASE,	\
-		.iomem_reg_shift =	0,			\
-		.io_type =		SERIAL_IO_MEM,		\
-		.irq =			INT_UART2,		\
-		.flags =			STD_COM_FLAGS,		\
-	}
-
-#else
-
-#define RS_TABLE_SIZE	3
-
-#define STD_COM_FLAGS	(ASYNC_SKIP_TEST)
-
-#define STD_SERIAL_PORT_DEFNS	\
-	{	\
-		.uart =			PORT_OMAP,		\
-		.baud_base =		BASE_BAUD,		\
-		.iomem_base =		OMAP1510_UART1_BASE,	\
-		.iomem_reg_shift =	2,			\
-		.io_type =		SERIAL_IO_MEM,		\
-		.irq =			INT_UART1,		\
-		.flags =		STD_COM_FLAGS,		\
-	}, {	\
-		.uart =			PORT_OMAP,		\
-		.baud_base =		BASE_BAUD,		\
-		.iomem_base =		OMAP1510_UART2_BASE,	\
-		.iomem_reg_shift =	2,			\
-		.io_type =		SERIAL_IO_MEM,		\
-		.irq =			INT_UART2,		\
-		.flags =		STD_COM_FLAGS,		\
-	}, {	\
-		.uart =			PORT_OMAP,		\
-		.baud_base =		BASE_BAUD,		\
-		.iomem_base =		OMAP1510_UART3_BASE,	\
-		.iomem_reg_shift =	2,			\
-		.io_type =		SERIAL_IO_MEM,		\
-		.irq =			INT_UART3,		\
-		.flags =		STD_COM_FLAGS,		\
-	}
-#endif				/* CONFIG_ARCH_OMAP730 */
-
-#define EXTRA_SERIAL_PORT_DEFNS
+#define OMAP1510_BASE_BAUD	(12000000/16)
+#define OMAP1610_BASE_BAUD	(48000000/16)
 
 /* OMAP FCR trigger  redefinitions */
 #define UART_FCR_R_TRIGGER_8	0x00	/* Mask for receive trigger set at 8 */
@@ -163,5 +44,9 @@
 #define UART_FCR_T_TRIGGER_32	0x20	/* Mask for transmit trigger set at 32 */
 #define UART_FCR_T_TRIGGER_56	0x30	/* Mask for transmit trigger set at 56 */
 
+#define STD_SERIAL_PORT_DEFNS
+#define EXTRA_SERIAL_PORT_DEFNS
+#define BASE_BAUD 0
+
 #endif	/* __ASSEMBLY__ */
 #endif	/* __ASM_ARCH_SERIAL_H */

include/asm-arm/arch-omap/system.h

@@ -14,7 +14,7 @@ static inline void arch_idle(void)
 
 static inline void arch_reset(char mode)
 {
-	*(volatile u16 *)(ARM_RSTCT1) = 1;
+	omap_writew(1, ARM_RSTCT1);
 }
 
 #endif

include/asm-arm/arch-omap/time.h

@@ -51,16 +51,16 @@ typedef struct {
 } mputimer_regs_t;
 
 #define mputimer_base(n) \
-    ((volatile mputimer_regs_t*)(OMAP_MPUTIMER_BASE + \
+    ((volatile mputimer_regs_t*)IO_ADDRESS(OMAP_MPUTIMER_BASE + \
 				 (n)*OMAP_MPUTIMER_OFF))
 
 static inline unsigned long timer32k_read(int reg) {
 	unsigned long val;
-	val = (inw(IO_ADDRESS((reg) + OMAP_32kHz_TIMER_BASE)));
+	val = omap_readw(reg + OMAP_32kHz_TIMER_BASE);
 	return val;
 }
 static inline void timer32k_write(int reg,int val) {
-	outw( (val), (IO_ADDRESS( (reg) + OMAP_32kHz_TIMER_BASE)));
+	omap_writew(val, reg + OMAP_32kHz_TIMER_BASE);
 }
 
 /*

include/asm-arm/arch-omap/uncompress.h

@@ -24,6 +24,7 @@
 #include <asm/hardware.h>
 #include <asm/arch/serial.h>
 
+#define UART_OMAP_MDR1		0x08	/* mode definition register */
 
 #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
 
@@ -35,9 +36,12 @@ puts(const char *s)
 
 	/* Determine which serial port to use */
 	do {
-		if (machine_is_innovator()) {
+		if (machine_is_omap_innovator() || machine_is_omap_osk()) {
 			shift = 2;
-			uart = (volatile u8 *)(OMAP1510_UART1_BASE);
+			uart = (volatile u8 *)(OMAP_UART1_BASE);
+		} else if (machine_is_omap_perseus2()) {
+			shift = 0;
+			uart = (volatile u8 *)(OMAP_UART1_BASE);
 		} else {
 			/* Assume nothing for unknown machines.
 			 * Add an entry for your machine to select

include/asm-arm/arch-omap/vmalloc.h

@@ -30,3 +30,4 @@
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
 #define VMALLOC_END	  (PAGE_OFFSET + 0x10000000)
+