Commit a4a71701 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
Valleyview) in that for the period following the GPU restart after a
reset, there are no GT interrupts received. From Ville's notes, bit 0 in
the HWSTAM corresponds to the render interrupt, and if we unmask it we
do see immediate resumption of GT interrupt delivery (via the master irq
handler) after the reset.

v2: Limit the w/a to the render interrupt from rcs

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
Fixes: c5498089 ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
References: d420a50c ("drm/i915: Clean up the HWSTAM mess")
Testcase: igt/gem_eio/reset-stress
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180808105101.913-2-chris@chris-wilson.co.uk
parent c1e63f6d
...@@ -387,8 +387,18 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) ...@@ -387,8 +387,18 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = RING_HWS_PGA(engine->mmio_base); mmio = RING_HWS_PGA(engine->mmio_base);
} }
if (INTEL_GEN(dev_priv) >= 6) if (INTEL_GEN(dev_priv) >= 6) {
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); u32 mask = ~0u;
/*
* Keep the render interrupt unmasked as this papers over
* lost interrupts following a reset.
*/
if (engine->id == RCS)
mask &= ~BIT(0);
I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
}
I915_WRITE(mmio, engine->status_page.ggtt_offset); I915_WRITE(mmio, engine->status_page.ggtt_offset);
POSTING_READ(mmio); POSTING_READ(mmio);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment