Commit a86eb582 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter

drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5

I have no idea how that crept in, but we need to do the write from the
ring and this is a masked register. Two fixes in 1!

Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 35c8ce6a
...@@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) ...@@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
if (INTEL_REVID(dev) == SKL_REVID_A0 || if (INTEL_REVID(dev) == SKL_REVID_A0 ||
INTEL_REVID(dev) == SKL_REVID_B0) { INTEL_REVID(dev) == SKL_REVID_B0) {
/* /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */
* WaDisableDgMirrorFixInHalfSliceChicken5:skl WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
* This is a pre-production w/a. GEN9_DG_MIRROR_FIX_ENABLE);
*/
I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
~GEN9_DG_MIRROR_FIX_ENABLE);
} }
if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) { if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) {
......
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