Commit aad3d14d authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Add DP training pattern 3 for CHV

CHV supports DP training pattern 3. Add the required stuff.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent a5043453
...@@ -3489,6 +3489,8 @@ enum punit_power_well { ...@@ -3489,6 +3489,8 @@ enum punit_power_well {
#define DP_LINK_TRAIN_OFF (3 << 28) #define DP_LINK_TRAIN_OFF (3 << 28)
#define DP_LINK_TRAIN_MASK (3 << 28) #define DP_LINK_TRAIN_MASK (3 << 28)
#define DP_LINK_TRAIN_SHIFT 28 #define DP_LINK_TRAIN_SHIFT 28
#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
/* CPT Link training mode */ /* CPT Link training mode */
#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
......
...@@ -2959,7 +2959,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, ...@@ -2959,7 +2959,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
} }
} else { } else {
*DP &= ~DP_LINK_TRAIN_MASK; if (IS_CHERRYVIEW(dev))
*DP &= ~DP_LINK_TRAIN_MASK_CHV;
else
*DP &= ~DP_LINK_TRAIN_MASK;
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
case DP_TRAINING_PATTERN_DISABLE: case DP_TRAINING_PATTERN_DISABLE:
...@@ -2972,8 +2975,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, ...@@ -2972,8 +2975,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
*DP |= DP_LINK_TRAIN_PAT_2; *DP |= DP_LINK_TRAIN_PAT_2;
break; break;
case DP_TRAINING_PATTERN_3: case DP_TRAINING_PATTERN_3:
DRM_ERROR("DP training pattern 3 not supported\n"); if (IS_CHERRYVIEW(dev)) {
*DP |= DP_LINK_TRAIN_PAT_2; *DP |= DP_LINK_TRAIN_PAT_3_CHV;
} else {
DRM_ERROR("DP training pattern 3 not supported\n");
*DP |= DP_LINK_TRAIN_PAT_2;
}
break; break;
} }
} }
...@@ -3260,7 +3267,10 @@ intel_dp_link_down(struct intel_dp *intel_dp) ...@@ -3260,7 +3267,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
DP &= ~DP_LINK_TRAIN_MASK_CPT; DP &= ~DP_LINK_TRAIN_MASK_CPT;
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
} else { } else {
DP &= ~DP_LINK_TRAIN_MASK; if (IS_CHERRYVIEW(dev))
DP &= ~DP_LINK_TRAIN_MASK_CHV;
else
DP &= ~DP_LINK_TRAIN_MASK;
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
} }
POSTING_READ(intel_dp->output_reg); POSTING_READ(intel_dp->output_reg);
......
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