Commit ad67ef68 authored by Paul Walmsley's avatar Paul Walmsley Committed by Tony Lindgren

ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain code

This patch creates an interface to the powerdomain registers in the
PRM/CM modules on OMAP2/3.  This interface is intended to be used by
PM code, e.g., pm.c; not by device drivers directly.

Each powerdomain will be defined in later patches as static
structures.  Also defined are dependencies between powerdomains,
used for adding and removing PM_WKDEP and CM_SLEEPDEP bits.  The
powerdomain structures are linked into a list at boot by
pwrdm_register(), similar to the OMAP clock code.

The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which
when enabled will emit verbose debug messages via pr_debug().
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>


parent 1fca2542
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
# Common support # Common support
obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
devices.o serial.o gpmc.o timer-gp.o devices.o serial.o gpmc.o timer-gp.o powerdomain.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......
...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk) ...@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask), v = __raw_readl(dd->control_reg);
dd->control_reg); v &= ~dd->enable_mask;
v |= clken_bits << __ffs(dd->enable_mask);
__raw_writel(v, dd->control_reg);
} }
/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) ...@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
state <<= dd->idlest_bit; state <<= dd->idlest_bit;
idlest_mask = 1 << dd->idlest_bit; idlest_mask = 1 << dd->idlest_bit;
while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) && while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
i < MAX_DPLL_WAIT_TRIES) { i < MAX_DPLL_WAIT_TRIES) {
i++; i++;
udelay(1); udelay(1);
...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
dd = clk->dpll_data; dd = clk->dpll_data;
v = cm_read_reg(dd->autoidle_reg); v = __raw_readl(dd->autoidle_reg);
v &= dd->autoidle_mask; v &= dd->autoidle_mask;
v >>= __ffs(dd->autoidle_mask); v >>= __ffs(dd->autoidle_mask);
...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk) ...@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
static void omap3_dpll_allow_idle(struct clk *clk) static void omap3_dpll_allow_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
* by writing 0x5 instead of 0x1. Add some mechanism to * by writing 0x5 instead of 0x1. Add some mechanism to
* optionally enter this mode. * optionally enter this mode.
*/ */
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/** /**
...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk) ...@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
static void omap3_dpll_deny_idle(struct clk *clk) static void omap3_dpll_deny_idle(struct clk *clk)
{ {
const struct dpll_data *dd; const struct dpll_data *dd;
u32 v;
if (!clk || !clk->dpll_data) if (!clk || !clk->dpll_data)
return; return;
dd = clk->dpll_data; dd = clk->dpll_data;
cm_rmw_reg_bits(dd->autoidle_mask, v = __raw_readl(dd->autoidle_reg);
DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask), v &= ~dd->autoidle_mask;
dd->autoidle_reg); v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
__raw_writel(v, dd->autoidle_reg);
} }
/* Clock control for DPLL outputs */ /* Clock control for DPLL outputs */
......
This diff is collapsed.
...@@ -29,6 +29,18 @@ config OMAP_DEBUG_LEDS ...@@ -29,6 +29,18 @@ config OMAP_DEBUG_LEDS
depends on OMAP_DEBUG_DEVICES depends on OMAP_DEBUG_DEVICES
default y if LEDS || LEDS_OMAP_DEBUG default y if LEDS || LEDS_OMAP_DEBUG
config OMAP_DEBUG_POWERDOMAIN
bool "Emit debug messages from powerdomain layer"
depends on ARCH_OMAP2 || ARCH_OMAP3
default n
help
Say Y here if you want to compile in powerdomain layer
debugging messages for OMAP2/3. These messages can
provide more detail as to why some powerdomain calls
may be failing, and will also emit a descriptive message
for every powerdomain register write. However, the
extra detail costs some memory.
config OMAP_RESET_CLOCKS config OMAP_RESET_CLOCKS
bool "Reset unused clocks during boot" bool "Reset unused clocks during boot"
depends on ARCH_OMAP depends on ARCH_OMAP
......
/*
* OMAP2/3 powerdomain control
*
* Copyright (C) 2007-8 Texas Instruments, Inc.
* Copyright (C) 2007-8 Nokia Corporation
*
* Written by Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
#include <linux/types.h>
#include <linux/list.h>
#include <asm/atomic.h>
#include <mach/cpu.h>
/* Powerdomain basic power states */
#define PWRDM_POWER_OFF 0x0
#define PWRDM_POWER_RET 0x1
#define PWRDM_POWER_INACTIVE 0x2
#define PWRDM_POWER_ON 0x3
/* Powerdomain allowable state bitfields */
#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_ON))
#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
(1 << PWRDM_POWER_RET))
#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
/*
* Number of memory banks that are power-controllable. On OMAP3430, the
* maximum is 4.
*/
#define PWRDM_MAX_MEM_BANKS 4
/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 100000
struct powerdomain;
/* Encodes dependencies between powerdomains - statically defined */
struct pwrdm_dep {
/* Powerdomain name */
const char *pwrdm_name;
/* Powerdomain pointer - resolved by the powerdomain code */
struct powerdomain *pwrdm;
/* Flags to mark OMAP chip restrictions, etc. */
const struct omap_chip_id omap_chip;
};
struct powerdomain {
/* Powerdomain name */
const char *name;
/* the address offset from CM_BASE/PRM_BASE */
const s16 prcm_offs;
/* Used to represent the OMAP chip types containing this pwrdm */
const struct omap_chip_id omap_chip;
/* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
const u8 dep_bit;
/* Powerdomains that can be told to wake this powerdomain up */
struct pwrdm_dep *wkdep_srcs;
/* Powerdomains that can be told to keep this pwrdm from inactivity */
struct pwrdm_dep *sleepdep_srcs;
/* Possible powerdomain power states */
const u8 pwrsts;
/* Possible logic power states when pwrdm in RETENTION */
const u8 pwrsts_logic_ret;
/* Number of software-controllable memory banks in this powerdomain */
const u8 banks;
/* Possible memory bank pwrstates when pwrdm in RETENTION */
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
/* Possible memory bank pwrstates when pwrdm is ON */
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
struct list_head node;
};
void pwrdm_init(struct powerdomain **pwrdm_list);
int pwrdm_register(struct powerdomain *pwrdm);
int pwrdm_unregister(struct powerdomain *pwrdm);
struct powerdomain *pwrdm_lookup(const char *name);
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm));
int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
int pwrdm_wait_transition(struct powerdomain *pwrdm);
#endif
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