Commit ad933b56 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Parametrize PANEL_PORT_SELECT_VLV

Passing the port as a parameter to PANEL_PORT_SELECT_VLV results in
neater code. Sadly the PCH port select bits aren't suitable for the
same treatment and the resulting macro would be much uglier, so
leave those defines as is.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2d965536
...@@ -5353,8 +5353,7 @@ enum punit_power_well { ...@@ -5353,8 +5353,7 @@ enum punit_power_well {
#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) #define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) #define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
#define PANEL_PORT_SELECT_DPB_VLV (1 << 30) #define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) #define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) #define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
......
...@@ -308,9 +308,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) ...@@ -308,9 +308,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
PANEL_PORT_SELECT_MASK; PANEL_PORT_SELECT_MASK;
if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) if (port_sel == PANEL_PORT_SELECT_VLV(port))
return pipe;
if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
return pipe; return pipe;
} }
...@@ -4327,6 +4325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, ...@@ -4327,6 +4325,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
u32 pp_on, pp_off, pp_div, port_sel = 0; u32 pp_on, pp_off, pp_div, port_sel = 0;
int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
int pp_on_reg, pp_off_reg, pp_div_reg; int pp_on_reg, pp_off_reg, pp_div_reg;
enum port port = dp_to_dig_port(intel_dp)->port;
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
pp_on_reg = PCH_PP_ON_DELAYS; pp_on_reg = PCH_PP_ON_DELAYS;
...@@ -4361,12 +4360,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, ...@@ -4361,12 +4360,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
/* Haswell doesn't have any port selection bits for the panel /* Haswell doesn't have any port selection bits for the panel
* power sequencer any more. */ * power sequencer any more. */
if (IS_VALLEYVIEW(dev)) { if (IS_VALLEYVIEW(dev)) {
if (dp_to_dig_port(intel_dp)->port == PORT_B) port_sel = PANEL_PORT_SELECT_VLV(port);
port_sel = PANEL_PORT_SELECT_DPB_VLV;
else
port_sel = PANEL_PORT_SELECT_DPC_VLV;
} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
if (dp_to_dig_port(intel_dp)->port == PORT_A) if (port == PORT_A)
port_sel = PANEL_PORT_SELECT_DPA; port_sel = PANEL_PORT_SELECT_DPA;
else else
port_sel = PANEL_PORT_SELECT_DPD; port_sel = PANEL_PORT_SELECT_DPD;
......
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