Commit aed1baf1 authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville

ath9k_hw: remove wrapper ath9k_hw_write_regs()

This is used only once by ath9k_hw_process_ini() to
write an array of phy registers through REG_WRITE_ARRAY(),
but we already call REG_WRITE_ARRAY() multiple times
on the same caller so just remove this pointless wrapper.
We'll eventually just move the ath9k_hw_process_ini()
caller as an callback to abstract away between different
hardware families.

Although this change is subtle I should note that this
does change the delay pattern on writing the next series
of registers. REG_WRITE_ARRAY() uses a counter for each
register write and does a udelay(1) every 64 writes. By
removing this call it means that the counter is processed
for all the iniBB_RfGain registers and is incremented
on ath9k_hw_process_ini(), before this the after the call
ath9k_hw_write_regs() was made the register counter was
kept at the same index number prior to the call.
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 42d5bc3f
...@@ -1483,7 +1483,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ...@@ -1483,7 +1483,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
modesIndex, regWrites); modesIndex, regWrites);
} }
ath9k_hw_write_regs(ah, freqIndex, regWrites); REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
......
...@@ -41,21 +41,6 @@ ...@@ -41,21 +41,6 @@
#include "hw.h" #include "hw.h"
/**
* ath9k_hw_write_regs - ??
*
* @ah: atheros hardware structure
* @freqIndex:
* @regWrites:
*
* Used for both the chipsets with an external AR2133/AR5133 radios and
* single-chip devices.
*/
void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites)
{
REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
}
/** /**
* ath9k_hw_ar9280_set_channel - set channel on single-chip device * ath9k_hw_ar9280_set_channel - set channel on single-chip device
* @ah: atheros hardware structure * @ah: atheros hardware structure
......
...@@ -17,9 +17,6 @@ ...@@ -17,9 +17,6 @@
#ifndef PHY_H #ifndef PHY_H
#define PHY_H #define PHY_H
/* Common between single chip and non single-chip solutions */
void ath9k_hw_write_regs(struct ath_hw *ah, u32 freqIndex, int regWrites);
/* Single chip radio settings */ /* Single chip radio settings */
int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
......
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